SG148921A1 - Fabrication of self-aligned via holes in polymer thin films - Google Patents

Fabrication of self-aligned via holes in polymer thin films

Info

Publication number
SG148921A1
SG148921A1 SG200803774-9A SG2008037749A SG148921A1 SG 148921 A1 SG148921 A1 SG 148921A1 SG 2008037749 A SG2008037749 A SG 2008037749A SG 148921 A1 SG148921 A1 SG 148921A1
Authority
SG
Singapore
Prior art keywords
self
dielectric
fabrication
via holes
thin films
Prior art date
Application number
SG200803774-9A
Other languages
English (en)
Inventor
Siddharth Mohapatra
Klaus Dimmler
Patrick H Jenkins
Original Assignee
Weyerhaeuser Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Weyerhaeuser Co filed Critical Weyerhaeuser Co
Publication of SG148921A1 publication Critical patent/SG148921A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
SG200803774-9A 2007-06-18 2008-05-16 Fabrication of self-aligned via holes in polymer thin films SG148921A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/764,326 US7858513B2 (en) 2007-06-18 2007-06-18 Fabrication of self-aligned via holes in polymer thin films

Publications (1)

Publication Number Publication Date
SG148921A1 true SG148921A1 (en) 2009-01-29

Family

ID=39791013

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200803774-9A SG148921A1 (en) 2007-06-18 2008-05-16 Fabrication of self-aligned via holes in polymer thin films

Country Status (6)

Country Link
US (1) US7858513B2 (ko)
EP (1) EP2006930A3 (ko)
JP (2) JP2008311630A (ko)
KR (1) KR100956253B1 (ko)
CN (1) CN101330130B (ko)
SG (1) SG148921A1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888169B2 (en) * 2007-12-26 2011-02-15 Organicid, Inc. Organic semiconductor device and method of manufacturing the same
US7718466B2 (en) * 2008-07-11 2010-05-18 Organicid, Inc. Performance improvements of OFETs through use of field oxide to control ink flow
JP2011035037A (ja) 2009-07-30 2011-02-17 Sony Corp 回路基板の製造方法および回路基板
US8211782B2 (en) 2009-10-23 2012-07-03 Palo Alto Research Center Incorporated Printed material constrained by well structures
US9059257B2 (en) 2013-09-30 2015-06-16 International Business Machines Corporation Self-aligned vias formed using sacrificial metal caps
CN107850958B (zh) 2015-06-30 2021-08-31 3M创新有限公司 图案化外覆层
US10361128B2 (en) 2017-01-11 2019-07-23 International Business Machines Corporation 3D vertical FET with top and bottom gate contacts
US20200185322A1 (en) * 2018-12-07 2020-06-11 Texas Instruments Incorporated Semiconductor device connections with sintered nanoparticles
KR20210011715A (ko) 2019-07-23 2021-02-02 박상태 회전 및 길이 조절이 가능한 탈부착형 전기파리채
US11289375B2 (en) 2020-03-23 2022-03-29 International Business Machines Corporation Fully aligned interconnects with selective area deposition

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5948533A (en) * 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5130274A (en) * 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5849634A (en) * 1994-04-15 1998-12-15 Sharp Kk Method of forming silicide film on silicon with oxygen concentration below 1018 /cm3
US5774340A (en) * 1996-08-28 1998-06-30 International Business Machines Corporation Planar redistribution structure and printed wiring device
US6277728B1 (en) * 1997-06-13 2001-08-21 Micron Technology, Inc. Multilevel interconnect structure with low-k dielectric and method of fabricating the structure
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
CA2306384A1 (en) * 1997-10-14 1999-04-22 Patterning Technologies Limited Method of forming an electronic device
US6015751A (en) * 1998-04-06 2000-01-18 Taiwan Semiconductor Manufacturing Company Self-aligned connection to underlayer metal lines through unlanded via holes
JP3439144B2 (ja) * 1998-12-22 2003-08-25 三洋電機株式会社 半導体装置およびその製造方法
US6159839A (en) * 1999-02-11 2000-12-12 Vanguard International Semiconductor Corporation Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections
US6187668B1 (en) * 1999-07-06 2001-02-13 United Microelectronics Corp. Method of forming self-aligned unlanded via holes
AU779878B2 (en) * 1999-12-21 2005-02-17 Flexenable Limited Forming interconnects
JP2001267417A (ja) * 2000-03-23 2001-09-28 Sanyo Electric Co Ltd 半導体装置の製造方法
US6635566B1 (en) * 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
US6413852B1 (en) * 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
JP2002110679A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
JP2002299442A (ja) * 2001-03-30 2002-10-11 Seiko Epson Corp 半導体装置の製造方法
JP2002313757A (ja) * 2001-04-17 2002-10-25 Hitachi Ltd 半導体集積回路装置の製造方法
DE10200399B4 (de) * 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
CN1237855C (zh) 2002-06-24 2006-01-18 威盛电子股份有限公司 用印刷方式制作电路基板导通孔及线路的方法
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US6924222B2 (en) * 2002-11-21 2005-08-02 Intel Corporation Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
US6861332B2 (en) * 2002-11-21 2005-03-01 Intel Corporation Air gap interconnect method
JP2005032769A (ja) 2003-07-07 2005-02-03 Seiko Epson Corp 多層配線の形成方法、配線基板の製造方法、デバイスの製造方法
JP4619060B2 (ja) * 2003-08-15 2011-01-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2005079288A (ja) * 2003-08-29 2005-03-24 Seiko Epson Corp 多層配線の形成方法および電子デバイス
JP2005142277A (ja) * 2003-11-05 2005-06-02 Seiko Epson Corp パターンの形成方法、電気光学装置の製造方法、デバイスの製造方法、電子機器
JP4684625B2 (ja) * 2003-11-14 2011-05-18 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7084479B2 (en) * 2003-12-08 2006-08-01 International Business Machines Corporation Line level air gaps
US20050170643A1 (en) * 2004-01-29 2005-08-04 Semiconductor Energy Laboratory Co., Ltd. Forming method of contact hole, and manufacturing method of semiconductor device, liquid crystal display device and EL display device
JP4281584B2 (ja) * 2004-03-04 2009-06-17 セイコーエプソン株式会社 半導体装置の製造方法
CN1743928A (zh) * 2004-08-30 2006-03-08 财团法人工业技术研究院 上发光型有机发光二极管像素的制造方法及其结构
GB2418062A (en) 2004-09-03 2006-03-15 Seiko Epson Corp An organic Field-Effect Transistor with a charge transfer injection layer
TWI237857B (en) * 2004-10-21 2005-08-11 Nanya Technology Corp Method of fabricating MOS transistor by millisecond anneal
US7306969B2 (en) * 2005-07-22 2007-12-11 Xerox Corporation Methods to minimize contact resistance
KR20070014579A (ko) * 2005-07-29 2007-02-01 삼성전자주식회사 유기 박막 트랜지스터 표시판 및 그 제조 방법
KR101219046B1 (ko) * 2005-11-17 2013-01-08 삼성디스플레이 주식회사 표시장치와 이의 제조방법
KR100659112B1 (ko) 2005-11-22 2006-12-19 삼성에스디아이 주식회사 유기 박막 트랜지스터 및 이의 제조 방법, 이를 구비한평판 디스플레이 장치
KR100766318B1 (ko) * 2005-11-29 2007-10-11 엘지.필립스 엘시디 주식회사 유기 반도체 물질을 이용한 박막트랜지스터와 이를 구비한액정표시장치용 어레이 기판 및 그 제조방법
KR100730183B1 (ko) 2005-12-12 2007-06-19 삼성에스디아이 주식회사 유기 박막 트랜지스터 및 이의 제조 방법, 이를 구비한평판표시장치

Also Published As

Publication number Publication date
KR20080111386A (ko) 2008-12-23
JP2008311630A (ja) 2008-12-25
JP2012156543A (ja) 2012-08-16
JP5638565B2 (ja) 2014-12-10
CN101330130A (zh) 2008-12-24
US7858513B2 (en) 2010-12-28
EP2006930A3 (en) 2011-03-23
EP2006930A2 (en) 2008-12-24
KR100956253B1 (ko) 2010-05-06
CN101330130B (zh) 2011-02-02
US20080311698A1 (en) 2008-12-18

Similar Documents

Publication Publication Date Title
SG148921A1 (en) Fabrication of self-aligned via holes in polymer thin films
JP2013506958A5 (ko)
EP2312620A4 (en) FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
TW200601458A (en) Microelectronic devices and fabrication methods thereof
WO2011066579A3 (en) Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions
TW200731889A (en) Method of fabricating substrate with embedded component therein
CN107331670A (zh) 显示面板及其制作方法、显示设备
EP2469591A3 (en) Method for fabricating a semiconductor device package
TWI616010B (zh) 導電基板及其製備方法
WO2007004115A3 (en) Organic electronic device and method for manufacture thereof
TW200944072A (en) Method for manufacturing a substrate having embedded component therein
US7390752B2 (en) Self-aligning patterning method
TW200802747A (en) The structure of embedded chip packaging and the fabricating method thereof
WO2010081073A3 (en) Passive electrical devices and methods of fabricating passive electrical devices
WO2010036776A3 (en) Thin film electronic devices with conductive and transparent gas and moisture permeation barriers
SG10201407347RA (en) Vias and conductive routing layers in semiconductor substrates
WO2008111309A1 (ja) 認識マークおよび回路基板の製造方法
CN103165679B (zh) 薄膜晶体管及其制造方法
MY161997A (en) Method for fabricating a heating element by depositing thin layers on an insulating substrate and the element thus obtained
TW200802701A (en) Interconnect structure, methods for fabricating the same, and methods for improving adhesion between low-k dielectric layers
TW200943430A (en) Method of fabricating semiconductor device
WO2010032975A3 (ko) 전도성 패턴의 제조방법 및 이에 의해 제조된 전도성 패턴
JP2010532578A5 (ko)
TWI256694B (en) Structure with embedded active components and manufacturing method thereof
SG159483A1 (en) Interconnects with improved tddb