SG145662A1 - Method for evaluation of bonded wafer - Google Patents
Method for evaluation of bonded waferInfo
- Publication number
- SG145662A1 SG145662A1 SG200801424-3A SG2008014243A SG145662A1 SG 145662 A1 SG145662 A1 SG 145662A1 SG 2008014243 A SG2008014243 A SG 2008014243A SG 145662 A1 SG145662 A1 SG 145662A1
- Authority
- SG
- Singapore
- Prior art keywords
- wafer
- etching
- active layer
- bonded wafer
- evaluation
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 238000011156 evaluation Methods 0.000 title abstract 2
- 238000005530 etching Methods 0.000 abstract 6
- 239000000463 material Substances 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007054480A JP5256625B2 (ja) | 2007-03-05 | 2007-03-05 | 貼り合わせウェーハの評価方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG145662A1 true SG145662A1 (en) | 2008-09-29 |
Family
ID=39472492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200801424-3A SG145662A1 (en) | 2007-03-05 | 2008-02-20 | Method for evaluation of bonded wafer |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7799655B2 (zh) |
| EP (1) | EP1968102B1 (zh) |
| JP (1) | JP5256625B2 (zh) |
| KR (1) | KR100969190B1 (zh) |
| CN (1) | CN100592489C (zh) |
| SG (1) | SG145662A1 (zh) |
| TW (1) | TWI390593B (zh) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105651582B (zh) * | 2015-12-30 | 2018-09-14 | 芜湖东旭光电装备技术有限公司 | 一种玻璃针状缺陷反射电镜样品的制作方法 |
| EP3916760B1 (en) * | 2020-05-28 | 2024-07-03 | Imec VZW | A method for producing an undercut in a 300 mm silicon-on-insulator platform |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2685819B2 (ja) * | 1988-03-31 | 1997-12-03 | 株式会社東芝 | 誘電体分離半導体基板とその製造方法 |
| JPH0719738B2 (ja) * | 1990-09-06 | 1995-03-06 | 信越半導体株式会社 | 接合ウェーハ及びその製造方法 |
| FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
| JPH0878298A (ja) * | 1994-09-09 | 1996-03-22 | Mitsubishi Materials Corp | シリコン半導体ウェーハ及びその製造方法 |
| US5888906A (en) * | 1996-09-16 | 1999-03-30 | Micron Technology, Inc. | Plasmaless dry contact cleaning method using interhalogen compounds |
| JPH1154579A (ja) * | 1997-07-31 | 1999-02-26 | Sumitomo Metal Ind Ltd | 半導体基板の評価方法 |
| JP2000031225A (ja) * | 1998-07-13 | 2000-01-28 | Sumitomo Metal Ind Ltd | 半導体基板の欠陥評価方法 |
| US7111629B2 (en) * | 2001-01-08 | 2006-09-26 | Apl Co., Ltd. | Method for cleaning substrate surface |
| US20030119278A1 (en) * | 2001-12-20 | 2003-06-26 | Mckinnell James C. | Substrates bonded with oxide affinity agent and bonding method |
| JP3760468B2 (ja) * | 2002-04-23 | 2006-03-29 | 信越半導体株式会社 | シリコン基板の評価方法 |
| US20040072446A1 (en) * | 2002-07-02 | 2004-04-15 | Applied Materials, Inc. | Method for fabricating an ultra shallow junction of a field effect transistor |
| US7153757B2 (en) * | 2002-08-29 | 2006-12-26 | Analog Devices, Inc. | Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure |
| US6818565B1 (en) * | 2002-09-24 | 2004-11-16 | Taiwan Semiconductor Manufacturing Company | Gate insulator pre-clean procedure |
| JP2004327595A (ja) * | 2003-04-23 | 2004-11-18 | Sumitomo Mitsubishi Silicon Corp | ピンホール欠陥の評価方法 |
| TWI228789B (en) * | 2004-01-20 | 2005-03-01 | Ind Tech Res Inst | Method for producing dielectric layer of high-k gate in MOST |
| US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
| JP4977999B2 (ja) * | 2005-11-21 | 2012-07-18 | 株式会社Ｓｕｍｃｏ | 貼合せ基板の製造方法及びその方法で製造された貼合せ基板 |
| KR20080073584A (ko) * | 2007-02-06 | 2008-08-11 | 주식회사 하이닉스반도체 | 실리콘 웨이퍼의 표면 검사 방법 |
-
2007
- 2007-03-05 JP JP2007054480A patent/JP5256625B2/ja active Active
-
2008
- 2008-02-14 TW TW097105193A patent/TWI390593B/zh active
- 2008-02-19 EP EP08003037A patent/EP1968102B1/en active Active
- 2008-02-20 SG SG200801424-3A patent/SG145662A1/en unknown
- 2008-02-25 US US12/037,057 patent/US7799655B2/en active Active
- 2008-03-05 KR KR1020080020727A patent/KR100969190B1/ko active IP Right Grant
- 2008-03-05 CN CN200810085603A patent/CN100592489C/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1968102A3 (en) | 2009-09-09 |
| KR100969190B1 (ko) | 2010-07-14 |
| US20080220589A1 (en) | 2008-09-11 |
| US7799655B2 (en) | 2010-09-21 |
| EP1968102B1 (en) | 2011-07-27 |
| CN100592489C (zh) | 2010-02-24 |
| CN101261949A (zh) | 2008-09-10 |
| EP1968102A2 (en) | 2008-09-10 |
| KR20080081860A (ko) | 2008-09-10 |
| TW200842935A (en) | 2008-11-01 |
| JP5256625B2 (ja) | 2013-08-07 |
| TWI390593B (zh) | 2013-03-21 |
| JP2008218739A (ja) | 2008-09-18 |
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