Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Recrystallisation Techniques (AREA)
• Element Separation (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Die Bonding (AREA)
• Laminated Bodies (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=36610717

Family Applications (1)

Country Status (9)

Families Citing this family (14)

Family Cites Families (4)

• 2006
  • 2006-03-31 DE DE602006000423T patent/DE602006000423T2/de active Active
  • 2006-03-31 EP EP06290542A patent/EP1840955B1/de active Active
  • 2006-03-31 AT AT06290542T patent/ATE383656T1/de not_active IP Right Cessation
  • 2006-06-21 US US11/472,745 patent/US7892861B2/en active Active
  • 2006-10-19 JP JP2006285168A patent/JP4723455B2/ja active Active
  • 2006-11-06 TW TW095141057A patent/TWI327745B/zh active
  • 2006-11-14 KR KR1020060112292A patent/KR100854800B1/ko active IP Right Grant
  • 2006-11-22 CN CNB2006101467596A patent/CN100547761C/zh active Active
  • 2006-11-23 SG SG200608167-3A patent/SG136024A1/en unknown

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