SG122926A1 - Structure and method of applying stresses to pfet and nfet transistor channels for improved performance - Google Patents
Structure and method of applying stresses to pfet and nfet transistor channels for improved performanceInfo
- Publication number
- SG122926A1 SG122926A1 SG200507470A SG200507470A SG122926A1 SG 122926 A1 SG122926 A1 SG 122926A1 SG 200507470 A SG200507470 A SG 200507470A SG 200507470 A SG200507470 A SG 200507470A SG 122926 A1 SG122926 A1 SG 122926A1
- Authority
- SG
- Singapore
- Prior art keywords
- pfet
- improved performance
- nfet transistor
- transistor channels
- applying stresses
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/904,808 US7193254B2 (en) | 2004-11-30 | 2004-11-30 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance |
Publications (1)
Publication Number | Publication Date |
---|---|
SG122926A1 true SG122926A1 (en) | 2006-06-29 |
Family
ID=36566550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200507470A SG122926A1 (en) | 2004-11-30 | 2005-11-24 | Structure and method of applying stresses to pfet and nfet transistor channels for improved performance |
Country Status (3)
Country | Link |
---|---|
US (2) | US7193254B2 (zh) |
CN (1) | CN100411175C (zh) |
SG (1) | SG122926A1 (zh) |
Families Citing this family (36)
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DE102004052578B4 (de) * | 2004-10-29 | 2009-11-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen einer unterschiedlichen mechanischen Verformung in unterschiedlichen Kanalgebieten durch Bilden eines Ätzstoppschichtstapels mit unterschiedlich modifizierter innerer Spannung |
US7193254B2 (en) * | 2004-11-30 | 2007-03-20 | International Business Machines Corporation | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance |
US7306983B2 (en) * | 2004-12-10 | 2007-12-11 | International Business Machines Corporation | Method for forming dual etch stop liner and protective layer in a semiconductor device |
US7432553B2 (en) * | 2005-01-19 | 2008-10-07 | International Business Machines Corporation | Structure and method to optimize strain in CMOSFETs |
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US7858458B2 (en) | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US7485521B2 (en) * | 2005-07-05 | 2009-02-03 | International Business Machines Corporation | Self-aligned dual stressed layers for NFET and PFET |
JP2007059473A (ja) * | 2005-08-22 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US7655991B1 (en) * | 2005-09-08 | 2010-02-02 | Xilinx, Inc. | CMOS device with stressed sidewall spacers |
US20070069307A1 (en) * | 2005-09-27 | 2007-03-29 | Kentaro Eda | Semiconductor device and method of manufacturing the same |
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US7541234B2 (en) * | 2005-11-03 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas |
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US7585720B2 (en) * | 2006-07-05 | 2009-09-08 | Toshiba America Electronic Components, Inc. | Dual stress liner device and method |
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US7732878B2 (en) * | 2006-10-18 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with continuous contact etch stop layer |
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US20080179684A1 (en) * | 2007-01-29 | 2008-07-31 | Chia-Wen Liang | Method of fabricating a strained silicon channel complementary metal oxide semiconductor transistor and structure thereof |
US7868390B2 (en) * | 2007-02-13 | 2011-01-11 | United Microelectronics Corp. | Method for fabricating strained-silicon CMOS transistor |
US20080237733A1 (en) * | 2007-03-27 | 2008-10-02 | International Business Machines Corporation | Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US7911001B2 (en) * | 2007-07-15 | 2011-03-22 | Samsung Electronics Co., Ltd. | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices |
US7982250B2 (en) * | 2007-09-21 | 2011-07-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
DE102008030852A1 (de) * | 2008-06-30 | 2010-01-07 | Advanced Micro Devices, Inc., Sunnyvale | Kontaktgräben zur besseren Verspannungsübertragung in Transistoren mit geringem Abstand |
US8236709B2 (en) | 2009-07-29 | 2012-08-07 | International Business Machines Corporation | Method of fabricating a device using low temperature anneal processes, a device and design structure |
DE102010028462B4 (de) * | 2010-04-30 | 2015-06-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verspannungsgedächtnistechnik mit geringerer Randzonenkapazität auf der Grundlage von Siliziumnitrid in MOS-Halbleiterbauelementen |
US8343825B2 (en) | 2011-01-19 | 2013-01-01 | International Business Machines Corporation | Reducing dislocation formation in semiconductor devices through targeted carbon implantation |
US8642424B2 (en) * | 2011-07-12 | 2014-02-04 | International Business Machines Corporation | Replacement metal gate structure and methods of manufacture |
US9716044B2 (en) * | 2011-08-18 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interlayer dielectric structure with high aspect ratio process (HARP) |
US8492208B1 (en) | 2012-01-05 | 2013-07-23 | International Business Machines Corporation | Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process |
CN102709194B (zh) * | 2012-06-21 | 2015-06-17 | 上海华力微电子有限公司 | Nmos器件制作方法 |
CN110137134B (zh) * | 2019-05-05 | 2021-02-09 | 中国科学院微电子研究所 | 互连结构、电路及包括该互连结构或电路的电子设备 |
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US7193254B2 (en) * | 2004-11-30 | 2007-03-20 | International Business Machines Corporation | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance |
-
2004
- 2004-11-30 US US10/904,808 patent/US7193254B2/en not_active Expired - Fee Related
-
2005
- 2005-08-23 CN CNB2005100915726A patent/CN100411175C/zh not_active Expired - Fee Related
- 2005-11-24 SG SG200507470A patent/SG122926A1/en unknown
-
2007
- 2007-01-24 US US11/657,154 patent/US7442611B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7442611B2 (en) | 2008-10-28 |
US20060113568A1 (en) | 2006-06-01 |
US20070122982A1 (en) | 2007-05-31 |
US7193254B2 (en) | 2007-03-20 |
CN1783496A (zh) | 2006-06-07 |
CN100411175C (zh) | 2008-08-13 |
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