SG11201906797WA - Mask-integrated surface protective tape, and method of producing a semiconductor chip using the same - Google Patents

Mask-integrated surface protective tape, and method of producing a semiconductor chip using the same

Info

Publication number
SG11201906797WA
SG11201906797WA SG11201906797WA SG11201906797WA SG11201906797WA SG 11201906797W A SG11201906797W A SG 11201906797WA SG 11201906797W A SG11201906797W A SG 11201906797WA SG 11201906797W A SG11201906797W A SG 11201906797WA SG 11201906797W A SG11201906797W A SG 11201906797WA
Authority
SG
Singapore
Prior art keywords
mask
semiconductor chip
producing
surface protective
protective tape
Prior art date
Application number
SG11201906797WA
Other languages
English (en)
Inventor
Akira Akutsu
Tomoaki Uchiyama
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Publication of SG11201906797WA publication Critical patent/SG11201906797WA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/02—Physical, chemical or physicochemical properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Adhesive Tapes (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Drying Of Semiconductors (AREA)
SG11201906797WA 2017-02-24 2018-02-22 Mask-integrated surface protective tape, and method of producing a semiconductor chip using the same SG11201906797WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017034164 2017-02-24
PCT/JP2018/006503 WO2018155569A1 (ja) 2017-02-24 2018-02-22 マスク一体型表面保護テープおよびそれを用いる半導体チップの製造方法

Publications (1)

Publication Number Publication Date
SG11201906797WA true SG11201906797WA (en) 2019-08-27

Family

ID=63252798

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201906797WA SG11201906797WA (en) 2017-02-24 2018-02-22 Mask-integrated surface protective tape, and method of producing a semiconductor chip using the same

Country Status (8)

Country Link
US (1) US11862504B2 (zh)
JP (1) JP7084306B2 (zh)
KR (2) KR102244291B1 (zh)
CN (1) CN109699189B (zh)
MY (1) MY195939A (zh)
SG (1) SG11201906797WA (zh)
TW (1) TWI680879B (zh)
WO (1) WO2018155569A1 (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7281873B2 (ja) 2018-05-14 2023-05-26 株式会社ディスコ ウェーハの加工方法
JP7154686B2 (ja) * 2018-06-06 2022-10-18 株式会社ディスコ ウェーハの加工方法
JP7143019B2 (ja) * 2018-06-06 2022-09-28 株式会社ディスコ ウェーハの加工方法
JP7143023B2 (ja) * 2018-08-06 2022-09-28 株式会社ディスコ ウェーハの加工方法
JP7154698B2 (ja) * 2018-09-06 2022-10-18 株式会社ディスコ ウェーハの加工方法
JP7175560B2 (ja) * 2018-09-06 2022-11-21 株式会社ディスコ ウェーハの加工方法
JP7166718B2 (ja) * 2018-10-17 2022-11-08 株式会社ディスコ ウェーハの加工方法
JP7171134B2 (ja) * 2018-10-17 2022-11-15 株式会社ディスコ ウェーハの加工方法
JP7503886B2 (ja) * 2018-11-06 2024-06-21 株式会社ディスコ ウェーハの加工方法
JP7199786B2 (ja) * 2018-11-06 2023-01-06 株式会社ディスコ ウェーハの加工方法
JP7251898B2 (ja) * 2018-12-06 2023-04-04 株式会社ディスコ ウェーハの加工方法
JP7246825B2 (ja) * 2018-12-06 2023-03-28 株式会社ディスコ ウェーハの加工方法
CN109671672A (zh) * 2018-12-06 2019-04-23 武汉华星光电半导体显示技术有限公司 一种柔性基板切割方法
JP7224719B2 (ja) * 2019-01-17 2023-02-20 株式会社ディスコ ウェーハの加工方法
JP7229636B2 (ja) * 2019-01-17 2023-02-28 株式会社ディスコ ウェーハの加工方法
JP7282453B2 (ja) * 2019-02-15 2023-05-29 株式会社ディスコ ウェーハの加工方法
JP7282452B2 (ja) * 2019-02-15 2023-05-29 株式会社ディスコ ウェーハの加工方法
JP7277019B2 (ja) * 2019-03-05 2023-05-18 株式会社ディスコ ウェーハの加工方法
JP7282455B2 (ja) * 2019-03-05 2023-05-29 株式会社ディスコ ウェーハの加工方法
JP7313767B2 (ja) * 2019-04-10 2023-07-25 株式会社ディスコ ウェーハの加工方法
JP2020174100A (ja) * 2019-04-10 2020-10-22 株式会社ディスコ ウェーハの加工方法
TWI797532B (zh) * 2020-12-31 2023-04-01 創技工業股份有限公司 半導體加工的方法及裝置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114124A (ja) * 1986-10-31 1988-05-19 Res Dev Corp Of Japan Ｘ線マスク用メンブレンおよび製造法
JP4333649B2 (ja) 2005-07-11 2009-09-16 パナソニック株式会社 半導体チップの製造方法
JP5064985B2 (ja) * 2006-12-05 2012-10-31 古河電気工業株式会社 半導体ウェハの処理方法
JP6045773B2 (ja) * 2009-11-26 2016-12-14 日立化成株式会社 接着シート及びその製造方法、並びに、半導体装置の製造方法及び半導体装置
JP2015052836A (ja) * 2013-09-05 2015-03-19 凸版印刷株式会社 透明導電性積層体の製造方法
JP6395586B2 (ja) * 2014-12-15 2018-09-26 株式会社ディスコ 被加工物の分割方法
JP6522998B2 (ja) * 2015-03-13 2019-05-29 古河電気工業株式会社 半導体ウェハの処理方法、半導体チップおよび半導体ウェハ処理用表面保護テープ。
JP6034522B1 (ja) 2016-03-17 2016-11-30 古河電気工業株式会社 半導体ウェハ加工用粘着テープおよび半導体ウェハの加工方法
JP6782215B2 (ja) * 2017-10-18 2020-11-11 古河電気工業株式会社 プラズマダイシング用マスク材、マスク一体型表面保護テープおよび半導体チップの製造方法

Also Published As

Publication number Publication date
JP7084306B2 (ja) 2022-06-14
CN109699189A (zh) 2019-04-30
JPWO2018155569A1 (ja) 2019-12-12
KR102244291B1 (ko) 2021-04-26
CN109699189B (zh) 2024-01-30
MY195939A (en) 2023-02-27
TW201840408A (zh) 2018-11-16
WO2018155569A1 (ja) 2018-08-30
KR20200108508A (ko) 2020-09-18
KR20190021447A (ko) 2019-03-05
US20190378747A1 (en) 2019-12-12
US11862504B2 (en) 2024-01-02
KR102191706B1 (ko) 2020-12-16
TWI680879B (zh) 2020-01-01

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