SG104917A1 - A method to fabricate a floating gate with a sloping sidewall for a flash memory - Google Patents

A method to fabricate a floating gate with a sloping sidewall for a flash memory

Info

Publication number
SG104917A1
SG104917A1 SG9903616A SG1999003616A SG104917A1 SG 104917 A1 SG104917 A1 SG 104917A1 SG 9903616 A SG9903616 A SG 9903616A SG 1999003616 A SG1999003616 A SG 1999003616A SG 104917 A1 SG104917 A1 SG 104917A1
Authority
SG
Singapore
Prior art keywords
fabricate
flash memory
floating gate
sloping sidewall
sloping
Prior art date
Application number
SG9903616A
Other languages
English (en)
Inventor
Komar N Chhagan Vijai
Ramachandramurthy Pr Yelehanka
Mei Sheng Zhou
Gerung Henry
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Publication of SG104917A1 publication Critical patent/SG104917A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • H01L29/7883Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
SG9903616A 1999-03-29 1999-07-21 A method to fabricate a floating gate with a sloping sidewall for a flash memory SG104917A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/280,023 US6284637B1 (en) 1999-03-29 1999-03-29 Method to fabricate a floating gate with a sloping sidewall for a flash memory

Publications (1)

Publication Number Publication Date
SG104917A1 true SG104917A1 (en) 2004-07-30

Family

ID=23071305

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9903616A SG104917A1 (en) 1999-03-29 1999-07-21 A method to fabricate a floating gate with a sloping sidewall for a flash memory

Country Status (3)

Country Link
US (2) US6284637B1 (de)
EP (1) EP1041642A1 (de)
SG (1) SG104917A1 (de)

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EP1113500B1 (de) * 1999-12-31 2008-05-07 STMicroelectronics S.r.l. Verfahren zum Herstellen nichtflüchtiger Speicherzellen
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KR100439025B1 (ko) * 2001-01-18 2004-07-03 삼성전자주식회사 플래쉬 메모리의 부유 전극의 형성 방법
US6551883B1 (en) * 2001-12-27 2003-04-22 Silicon Integrated Systems Corp. MOS device with dual gate insulators and method of forming the same
TW527652B (en) * 2002-02-06 2003-04-11 Taiwan Semiconductor Mfg Manufacturing method of selection gate for the split gate flash memory cell and its structure
KR100466192B1 (ko) * 2002-07-18 2005-01-13 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100523839B1 (ko) * 2002-10-07 2005-10-27 한국전자통신연구원 건식 리소그라피 방법 및 이를 이용한 게이트 패턴 형성방법
KR100707169B1 (ko) * 2003-12-12 2007-04-13 삼성전자주식회사 메모리 소자 및 그 제조 방법
KR100655289B1 (ko) * 2005-01-13 2006-12-08 삼성전자주식회사 플래시 메모리 제조 방법
KR100647001B1 (ko) * 2005-03-09 2006-11-23 주식회사 하이닉스반도체 플래쉬 메모리 소자의 플로팅 게이트 전극 형성방법
US20070037386A1 (en) * 2005-08-13 2007-02-15 Williams John L Sloped thin film substrate edges
KR100632651B1 (ko) * 2005-09-15 2006-10-11 주식회사 하이닉스반도체 플래쉬 메모리소자의 제조방법
KR100885791B1 (ko) * 2005-11-18 2009-02-26 주식회사 하이닉스반도체 낸드 플래쉬 메모리 소자의 제조방법
KR100661221B1 (ko) * 2005-12-30 2006-12-22 동부일렉트로닉스 주식회사 플래시 메모리의 제조 방법
KR101226974B1 (ko) * 2006-05-03 2013-01-28 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조 방법
US7582530B2 (en) * 2006-06-30 2009-09-01 Intel Corporation Managing floating gate-to-floating gate spacing to support scalability
KR100831275B1 (ko) * 2006-09-22 2008-05-22 동부일렉트로닉스 주식회사 플래시 메모리 소자의 제조 방법
US7863124B2 (en) * 2007-05-10 2011-01-04 International Business Machines Corporation Residue free patterned layer formation method applicable to CMOS structures
DE102014005879B4 (de) * 2014-04-16 2021-12-16 Infineon Technologies Ag Vertikale Halbleitervorrichtung
CN110828307A (zh) * 2019-10-16 2020-02-21 中芯集成电路制造(绍兴)有限公司 形成具有倾斜侧壁的材料层的方法及半导体器件

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Also Published As

Publication number Publication date
US6284637B1 (en) 2001-09-04
EP1041642A1 (de) 2000-10-04
US20020000604A1 (en) 2002-01-03

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