SG104917A1 - A method to fabricate a floating gate with a sloping sidewall for a flash memory - Google Patents
A method to fabricate a floating gate with a sloping sidewall for a flash memoryInfo
- Publication number
- SG104917A1 SG104917A1 SG9903616A SG1999003616A SG104917A1 SG 104917 A1 SG104917 A1 SG 104917A1 SG 9903616 A SG9903616 A SG 9903616A SG 1999003616 A SG1999003616 A SG 1999003616A SG 104917 A1 SG104917 A1 SG 104917A1
- Authority
- SG
- Singapore
- Prior art keywords
- fabricate
- flash memory
- floating gate
- sloping sidewall
- sloping
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/280,023 US6284637B1 (en) | 1999-03-29 | 1999-03-29 | Method to fabricate a floating gate with a sloping sidewall for a flash memory |
Publications (1)
Publication Number | Publication Date |
---|---|
SG104917A1 true SG104917A1 (en) | 2004-07-30 |
Family
ID=23071305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9903616A SG104917A1 (en) | 1999-03-29 | 1999-07-21 | A method to fabricate a floating gate with a sloping sidewall for a flash memory |
Country Status (3)
Country | Link |
---|---|
US (2) | US6284637B1 (de) |
EP (1) | EP1041642A1 (de) |
SG (1) | SG104917A1 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001035808A (ja) * | 1999-07-22 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法 |
KR100317488B1 (ko) * | 1999-12-28 | 2001-12-24 | 박종섭 | 플래쉬 메모리 소자의 제조 방법 |
EP1113500B1 (de) * | 1999-12-31 | 2008-05-07 | STMicroelectronics S.r.l. | Verfahren zum Herstellen nichtflüchtiger Speicherzellen |
US6521544B1 (en) * | 2000-08-31 | 2003-02-18 | Micron Technology, Inc. | Method of forming an ultra thin dielectric film |
KR100357692B1 (ko) * | 2000-10-27 | 2002-10-25 | 삼성전자 주식회사 | 비휘발성 메모리소자 및 그 제조방법 |
KR100439025B1 (ko) * | 2001-01-18 | 2004-07-03 | 삼성전자주식회사 | 플래쉬 메모리의 부유 전극의 형성 방법 |
US6551883B1 (en) * | 2001-12-27 | 2003-04-22 | Silicon Integrated Systems Corp. | MOS device with dual gate insulators and method of forming the same |
TW527652B (en) * | 2002-02-06 | 2003-04-11 | Taiwan Semiconductor Mfg | Manufacturing method of selection gate for the split gate flash memory cell and its structure |
KR100466192B1 (ko) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100523839B1 (ko) * | 2002-10-07 | 2005-10-27 | 한국전자통신연구원 | 건식 리소그라피 방법 및 이를 이용한 게이트 패턴 형성방법 |
KR100707169B1 (ko) * | 2003-12-12 | 2007-04-13 | 삼성전자주식회사 | 메모리 소자 및 그 제조 방법 |
KR100655289B1 (ko) * | 2005-01-13 | 2006-12-08 | 삼성전자주식회사 | 플래시 메모리 제조 방법 |
KR100647001B1 (ko) * | 2005-03-09 | 2006-11-23 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 플로팅 게이트 전극 형성방법 |
US20070037386A1 (en) * | 2005-08-13 | 2007-02-15 | Williams John L | Sloped thin film substrate edges |
KR100632651B1 (ko) * | 2005-09-15 | 2006-10-11 | 주식회사 하이닉스반도체 | 플래쉬 메모리소자의 제조방법 |
KR100885791B1 (ko) * | 2005-11-18 | 2009-02-26 | 주식회사 하이닉스반도체 | 낸드 플래쉬 메모리 소자의 제조방법 |
KR100661221B1 (ko) * | 2005-12-30 | 2006-12-22 | 동부일렉트로닉스 주식회사 | 플래시 메모리의 제조 방법 |
KR101226974B1 (ko) * | 2006-05-03 | 2013-01-28 | 엘지디스플레이 주식회사 | 액정표시장치용 어레이 기판 및 그 제조 방법 |
US7582530B2 (en) * | 2006-06-30 | 2009-09-01 | Intel Corporation | Managing floating gate-to-floating gate spacing to support scalability |
KR100831275B1 (ko) * | 2006-09-22 | 2008-05-22 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자의 제조 방법 |
US7863124B2 (en) * | 2007-05-10 | 2011-01-04 | International Business Machines Corporation | Residue free patterned layer formation method applicable to CMOS structures |
DE102014005879B4 (de) * | 2014-04-16 | 2021-12-16 | Infineon Technologies Ag | Vertikale Halbleitervorrichtung |
CN110828307A (zh) * | 2019-10-16 | 2020-02-21 | 中芯集成电路制造(绍兴)有限公司 | 形成具有倾斜侧壁的材料层的方法及半导体器件 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5957479A (ja) * | 1982-09-27 | 1984-04-03 | Mitsubishi Electric Corp | Mos形半導体不揮発性メモリ装置の製造方法 |
US4830974A (en) * | 1988-01-11 | 1989-05-16 | Atmel Corporation | EPROM fabrication process |
JPH01216577A (ja) * | 1988-02-24 | 1989-08-30 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPH0316181A (ja) * | 1988-10-14 | 1991-01-24 | Ricoh Co Ltd | フローティングゲート型半導体メモリ装置 |
JPH07263415A (ja) * | 1994-03-18 | 1995-10-13 | Fujitsu Ltd | 半導体装置の製造方法 |
TW318961B (de) | 1994-05-04 | 1997-11-01 | Nippon Precision Circuits | |
US5554564A (en) | 1994-08-01 | 1996-09-10 | Texas Instruments Incorporated | Pre-oxidizing high-dielectric-constant material electrodes |
US5550072A (en) * | 1994-08-30 | 1996-08-27 | National Semiconductor Corporation | Method of fabrication of integrated circuit chip containing EEPROM and capacitor |
US5573979A (en) | 1995-02-13 | 1996-11-12 | Texas Instruments Incorporated | Sloped storage node for a 3-D dram cell structure |
JP3484023B2 (ja) * | 1996-10-24 | 2004-01-06 | 株式会社東芝 | 半導体装置およびその製造方法 |
DE19652547C2 (de) * | 1996-12-17 | 2002-04-25 | Infineon Technologies Ag | Speicherzellenanordnung mit Grabenstruktur und einem Gatedielektrikum, das ein Material mit Ladungsträger-Haftstellen enthält, und Verfahren zu deren Herstellung |
US6063668A (en) * | 1997-12-18 | 2000-05-16 | Advanced Micro Devices, Inc. | Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices |
US5973353A (en) * | 1997-12-18 | 1999-10-26 | Advanced Micro Devices, Inc. | Methods and arrangements for forming a tapered floating gate in non-volatile memory semiconductor devices |
US6051451A (en) * | 1998-04-21 | 2000-04-18 | Advanced Micro Devices, Inc. | Heavy ion implant process to eliminate polystringers in high density type flash memory devices |
-
1999
- 1999-03-29 US US09/280,023 patent/US6284637B1/en not_active Expired - Fee Related
- 1999-07-21 SG SG9903616A patent/SG104917A1/en unknown
-
2000
- 2000-03-10 EP EP00640002A patent/EP1041642A1/de not_active Withdrawn
-
2001
- 2001-08-02 US US09/920,603 patent/US20020000604A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US6284637B1 (en) | 2001-09-04 |
EP1041642A1 (de) | 2000-10-04 |
US20020000604A1 (en) | 2002-01-03 |
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