SE466078B - Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningen - Google Patents
Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningenInfo
- Publication number
- SE466078B SE466078B SE9001403A SE9001403A SE466078B SE 466078 B SE466078 B SE 466078B SE 9001403 A SE9001403 A SE 9001403A SE 9001403 A SE9001403 A SE 9001403A SE 466078 B SE466078 B SE 466078B
- Authority
- SE
- Sweden
- Prior art keywords
- layer
- polycrystalline
- semiconductor
- ions
- doped
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/206—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of combinations of capacitors and resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9001403A SE466078B (sv) | 1990-04-20 | 1990-04-20 | Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningen |
| EP91850073A EP0453424B1 (de) | 1990-04-20 | 1991-03-20 | Integrierte Schaltungsanordnung mit Abschirmungsvorrichtung und Verfahren zu ihrer Herstellung |
| DE69109929T DE69109929T2 (de) | 1990-04-20 | 1991-03-20 | Integrierte Schaltungsanordnung mit Abschirmungsvorrichtung und Verfahren zu ihrer Herstellung. |
| US07/680,509 US5196723A (en) | 1990-04-20 | 1991-04-04 | Integrated circuit screen arrangement and a method for its manufacture |
| JP08801391A JP3311759B2 (ja) | 1990-04-20 | 1991-04-19 | スクリーン構造を有する集積回路およびその製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9001403A SE466078B (sv) | 1990-04-20 | 1990-04-20 | Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningen |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| SE9001403D0 SE9001403D0 (sv) | 1990-04-20 |
| SE9001403L SE9001403L (sv) | 1991-10-21 |
| SE466078B true SE466078B (sv) | 1991-12-09 |
Family
ID=20379222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE9001403A SE466078B (sv) | 1990-04-20 | 1990-04-20 | Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningen |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5196723A (de) |
| EP (1) | EP0453424B1 (de) |
| JP (1) | JP3311759B2 (de) |
| DE (1) | DE69109929T2 (de) |
| SE (1) | SE466078B (de) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541442A (en) * | 1994-08-31 | 1996-07-30 | International Business Machines Corporation | Integrated compact capacitor-resistor/inductor configuration |
| AU2187397A (en) | 1996-03-22 | 1997-10-10 | Telefonaktiebolaget Lm Ericsson (Publ) | Semiconductor device shielded by an array of electrically conducting pins and a method to manufacture such a device |
| SE511816C3 (sv) * | 1996-06-17 | 2000-01-24 | Ericsson Telefon Ab L M | Resistor innefattande en resistorkropp av polykristallint kisel samt foerfarande foer framstaellning av en saadan |
| WO1998049732A2 (en) * | 1997-04-28 | 1998-11-05 | Koninklijke Philips Electronics N.V. | Lateral mos transistor device |
| US6836022B2 (en) * | 2003-02-13 | 2004-12-28 | Medtronic, Inc. | High voltage flip-chip component package and method for forming the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4836598B1 (de) * | 1969-09-05 | 1973-11-06 | ||
| US3602782A (en) * | 1969-12-05 | 1971-08-31 | Thomas Klein | Conductor-insulator-semiconductor fieldeffect transistor with semiconductor layer embedded in dielectric underneath interconnection layer |
| US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
| US3787717A (en) * | 1971-12-09 | 1974-01-22 | Ibm | Over voltage protection circuit lateral bipolar transistor with gated collector junction |
| JPS55123157A (en) * | 1979-03-16 | 1980-09-22 | Oki Electric Ind Co Ltd | High-stability ion-injected resistor |
| US4430663A (en) * | 1981-03-25 | 1984-02-07 | Bell Telephone Laboratories, Incorporated | Prevention of surface channels in silicon semiconductor devices |
| US4613886A (en) * | 1981-07-09 | 1986-09-23 | Intel Corporation | CMOS static memory cell |
| US4764800A (en) * | 1986-05-07 | 1988-08-16 | Advanced Micro Devices, Inc. | Seal structure for an integrated circuit |
-
1990
- 1990-04-20 SE SE9001403A patent/SE466078B/sv unknown
-
1991
- 1991-03-20 EP EP91850073A patent/EP0453424B1/de not_active Expired - Lifetime
- 1991-03-20 DE DE69109929T patent/DE69109929T2/de not_active Expired - Fee Related
- 1991-04-04 US US07/680,509 patent/US5196723A/en not_active Expired - Lifetime
- 1991-04-19 JP JP08801391A patent/JP3311759B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| SE9001403D0 (sv) | 1990-04-20 |
| JP3311759B2 (ja) | 2002-08-05 |
| DE69109929D1 (de) | 1995-06-29 |
| SE9001403L (sv) | 1991-10-21 |
| JPH0661435A (ja) | 1994-03-04 |
| US5196723A (en) | 1993-03-23 |
| EP0453424A1 (de) | 1991-10-23 |
| EP0453424B1 (de) | 1995-05-24 |
| DE69109929T2 (de) | 1995-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5514612A (en) | Method of making a semiconductor device with integrated RC network and schottky diode | |
| EP0684643B1 (de) | Herstellungsmethode für Halbleiterelemente in einer aktiven Schicht auf einem Trägersubstrat | |
| US6797549B2 (en) | High voltage MOS transistor with gate extension | |
| EP0452829A2 (de) | Halbleiteranordnung mit verringten zeitabhängigen dielektrischen Fehlern | |
| WO1996003770A9 (en) | Semiconductor device with integrated rc network and schottky diode | |
| JPH0817694A (ja) | 集積回路に適用するための薄膜およびバルク混合半導体基板ならびにその形成方法 | |
| KR900003257B1 (ko) | 보호회로를 갖는 반도체장치 | |
| EP0870321B1 (de) | Dünnschichtkondensator, ESD-geschützte Dünnschichtkondensatorstruktur und entsprechende Herstellungsverfahren | |
| JP2872585B2 (ja) | 電界効果型トランジスタとその製造方法 | |
| US3509433A (en) | Contacts for buried layer in a dielectrically isolated semiconductor pocket | |
| CN100552919C (zh) | 半导体器件及其结构的制作方法 | |
| JPS6317560A (ja) | Mos型半導体装置 | |
| SE466078B (sv) | Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningen | |
| US20220189949A1 (en) | High reliability polysilicon components | |
| JPS59200457A (ja) | 集積された絶縁ゲ−ト電界効果トランジスタを有するモノリシツク集積回路の製造方法 | |
| US4285117A (en) | Method of manufacturing a device in a silicon wafer | |
| US5554549A (en) | Salicide process for FETs | |
| US12402390B2 (en) | Method of manufacturing silicon carbide semiconductor power device | |
| US20030168710A1 (en) | High voltage integrated circuit including bipolar transistor within high voltage island area | |
| US20100308416A1 (en) | Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection | |
| SE465193B (sv) | Foer hoegspaenning avsedd ic-krets | |
| JPS5837969A (ja) | 保護回路素子 | |
| KR100190467B1 (ko) | 반도체 장치 및 그 제조방법 | |
| JPH09129884A (ja) | Soi型薄膜電界効果トランジスタ及びその製造方法 | |
| Szeto | Integrated Circuits Laboratory, Hewlett Packard Laboratories, Palo Alto, California 94304 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| NAL | Patent in force |
Ref document number: 9001403-6 Format of ref document f/p: F |