SE428614B - Sett att tillverka en halvledaranordning bl a innefattande trimning av ett resistmonster - Google Patents

Sett att tillverka en halvledaranordning bl a innefattande trimning av ett resistmonster

Info

Publication number
SE428614B
SE428614B SE7612468A SE7612468A SE428614B SE 428614 B SE428614 B SE 428614B SE 7612468 A SE7612468 A SE 7612468A SE 7612468 A SE7612468 A SE 7612468A SE 428614 B SE428614 B SE 428614B
Authority
SE
Sweden
Prior art keywords
manufacture
semiconductor device
trimming
device including
resist sample
Prior art date
Application number
SE7612468A
Other languages
English (en)
Swedish (sv)
Other versions
SE7612468L (sv
Inventor
Yau L Dy
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of SE7612468L publication Critical patent/SE7612468L/xx
Publication of SE428614B publication Critical patent/SE428614B/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Bipolar Integrated Circuits (AREA)
SE7612468A 1975-11-20 1976-11-09 Sett att tillverka en halvledaranordning bl a innefattande trimning av ett resistmonster SE428614B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/633,602 US3997367A (en) 1975-11-20 1975-11-20 Method for making transistors

Publications (2)

Publication Number Publication Date
SE7612468L SE7612468L (sv) 1977-05-21
SE428614B true SE428614B (sv) 1983-07-11

Family

ID=24540323

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7612468A SE428614B (sv) 1975-11-20 1976-11-09 Sett att tillverka en halvledaranordning bl a innefattande trimning av ett resistmonster

Country Status (11)

Country Link
US (1) US3997367A (fr)
JP (1) JPS5264279A (fr)
BE (1) BE848345A (fr)
CA (1) CA1064164A (fr)
DE (1) DE2652253C2 (fr)
ES (1) ES453471A1 (fr)
FR (1) FR2332615A1 (fr)
GB (1) GB1562095A (fr)
IT (1) IT1064386B (fr)
NL (1) NL176818C (fr)
SE (1) SE428614B (fr)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4202002A (en) * 1977-01-19 1980-05-06 International Business Machines Corporation Ion-implanted layers with abrupt edges
US4070211A (en) * 1977-04-04 1978-01-24 The United States Of America As Represented By The Secretary Of The Navy Technique for threshold control over edges of devices on silicon-on-sapphire
NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
US4241165A (en) * 1978-09-05 1980-12-23 Motorola, Inc. Plasma development process for photoresist
US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
EP0057605B1 (fr) * 1981-01-29 1986-10-08 Sumitomo Electric Industries Limited Transistor à effet de champ à grille Schottky et son procédé de fabrication
US4472874A (en) * 1981-06-10 1984-09-25 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming planar isolation regions having field inversion regions
US4601095A (en) * 1981-10-27 1986-07-22 Sumitomo Electric Industries, Ltd. Process for fabricating a Schottky-barrier gate field effect transistor
US4585342A (en) * 1984-06-29 1986-04-29 International Business Machines Corporation System for real-time monitoring the characteristics, variations and alignment errors of lithography structures
IT1214805B (it) * 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
US4821094A (en) * 1985-11-08 1989-04-11 Lockheed Missiles & Space Company, Inc. Gate alignment procedure in fabricating semiconductor devices
DE3602461A1 (de) * 1986-01-28 1987-07-30 Telefunken Electronic Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
JPS63182860A (ja) * 1987-01-26 1988-07-28 Toshiba Corp 半導体装置とその製造方法
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
US4871684A (en) * 1987-10-29 1989-10-03 International Business Machines Corporation Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors
US5171718A (en) * 1987-11-27 1992-12-15 Sony Corporation Method for forming a fine pattern by using a patterned resist layer
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
US5064773A (en) * 1988-12-27 1991-11-12 Raytheon Company Method of forming bipolar transistor having closely spaced device regions
EP0394597A1 (fr) * 1989-04-28 1990-10-31 International Business Machines Corporation Système de suivi pour procédé d'attaque dans un équipement de RIE et sa application à la production de motifs reproductibles et à haute résolution
US5223914A (en) * 1989-04-28 1993-06-29 International Business Machines Corporation Follow-up system for etch process monitoring
KR960000225B1 (ko) * 1991-08-26 1996-01-03 가부시키가이샤 한도오따이 에네루기 겐큐쇼 절연게이트형 반도체장치의 제작방법
US5272095A (en) * 1992-03-18 1993-12-21 Research Triangle Institute Method of manufacturing heterojunction transistors with self-aligned metal contacts
US5318916A (en) * 1992-07-31 1994-06-07 Research Triangle Institute Symmetric self-aligned processing
JP3437863B2 (ja) * 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Ｍｉｓ型半導体装置の作製方法
TW297142B (fr) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
JP3030368B2 (ja) 1993-10-01 2000-04-10 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US6777763B1 (en) 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
US6232048B1 (en) 1996-12-31 2001-05-15 Advanced Micro Devices Method for preparing narrow photoresist lines
US6150072A (en) * 1997-08-22 2000-11-21 Siemens Microelectronics, Inc. Method of manufacturing a shallow trench isolation structure for a semiconductor device
US6069046A (en) * 1997-11-26 2000-05-30 Advanced Micro Devices, Inc. Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment
US6121155A (en) * 1998-12-04 2000-09-19 Advanced Micro Devices Integrated circuit fabrication critical dimension control using self-limiting resist etch
WO2000034437A2 (fr) * 1998-12-08 2000-06-15 Merck & Co., Inc. Inhibiteurs de prenyl-proteine transferase
US6444536B2 (en) * 1999-07-08 2002-09-03 Agere Systems Guardian Corp. Method for fabricating bipolar transistors
US6376308B1 (en) * 2000-01-19 2002-04-23 Advanced Micro Devices, Inc. Process for fabricating an EEPROM device having a pocket substrate region
US6168993B1 (en) * 2000-01-19 2001-01-02 Advanced Micro Devices, Inc. Process for fabricating a semiconductor device having a graded junction
US6255147B1 (en) * 2000-01-31 2001-07-03 Advanced Micro Devices, Inc. Silicon on insulator circuit structure with extra narrow field transistors and method of forming same
US6589709B1 (en) 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6716571B2 (en) * 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
US6815359B2 (en) * 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
US6828259B2 (en) 2001-03-28 2004-12-07 Advanced Micro Devices, Inc. Enhanced transistor gate using E-beam radiation
US6774365B2 (en) 2001-03-28 2004-08-10 Advanced Micro Devices, Inc. SEM inspection and analysis of patterned photoresist features
US6630288B2 (en) 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
AU2002309493A1 (en) * 2001-03-28 2002-10-08 Advanced Micro Devices, Inc. Method of forming enhanced transistor gate using e-beam radiation and integrated circuit including this transistor gate
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
US6573165B2 (en) * 2001-07-06 2003-06-03 Texas Instruments Incorporated Method of providing polysilicon spacer for implantation
US7179752B2 (en) * 2001-07-10 2007-02-20 Tokyo Electron Limited Dry etching method
US20030092281A1 (en) * 2001-11-13 2003-05-15 Chartered Semiconductors Manufactured Limited Method for organic barc and photoresist trimming process
US6586303B2 (en) * 2001-12-05 2003-07-01 United Microelectronics Corp. Method for fabricating a mask ROM
KR100486111B1 (ko) * 2002-07-10 2005-04-29 매그나칩 반도체 유한회사 반도체소자의 소자분리막 제조방법
KR100559994B1 (ko) * 2003-08-08 2006-03-13 동부아남반도체 주식회사 측벽 방식을 이용한 플래시 메모리의 플로팅 게이트 형성방법
US7288829B2 (en) * 2004-11-10 2007-10-30 International Business Machines Corporation Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide
FR3030876B1 (fr) 2014-12-22 2017-12-15 Commissariat Energie Atomique Procede de realisation de motifs

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3592707A (en) * 1968-06-17 1971-07-13 Bell Telephone Labor Inc Precision masking using silicon nitride and silicon oxide
US3816198A (en) * 1969-09-22 1974-06-11 G Babcock Selective plasma etching of organic materials employing photolithographic techniques
US3649393A (en) * 1970-06-12 1972-03-14 Ibm Variable depth etching of film layers using variable exposures of photoresists
US3890176A (en) * 1972-08-18 1975-06-17 Gen Electric Method for removing photoresist from substrate
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
SE405526B (sv) * 1973-07-16 1978-12-11 Western Electric Co Transistor och sett for dess tillverkning
JPS5034175A (fr) * 1973-07-27 1975-04-02

Also Published As

Publication number Publication date
US3997367A (en) 1976-12-14
NL7612850A (nl) 1977-05-24
JPS5264279A (en) 1977-05-27
NL176818C (nl) 1985-06-03
NL176818B (nl) 1985-01-02
GB1562095A (en) 1980-03-05
CA1064164A (fr) 1979-10-09
BE848345A (fr) 1977-03-16
JPS5724938B2 (fr) 1982-05-26
IT1064386B (it) 1985-02-18
FR2332615B1 (fr) 1980-09-12
DE2652253C2 (de) 1982-06-03
DE2652253A1 (de) 1977-06-02
ES453471A1 (es) 1977-11-16
SE7612468L (sv) 1977-05-21
FR2332615A1 (fr) 1977-06-17

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