RU2820562C1 - Gallium arsenide operational amplifier with high gain and low level of systematic component of zero offset voltage - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: into the gallium arsenide operational amplifier circuit are introduced first and second additional bipolar transistors, which combined emitters are connected to the gate of the additional field-effect transistor and through the additional resistor are connected to the combined bases of the output transistors of the intermediate stage, base of the first additional bipolar transistor is connected to the collector of the first output transistor of the intermediate stage and to the third reference current source, base of the second additional bipolar transistor is connected to the base of the second output transistor of the intermediate stage and to the fourth reference current source, collector of the first additional bipolar transistor is connected to the fifth reference current source and to the input of the current mirror of the intermediate stage, non-inverting output of which is connected to output of device, and the inverting output is connected to the collector of the second additional bipolar transistor, to the base of the output transistor and the sixth reference current source.

EFFECT: design of a precision operational amplifier circuit with a low level of a systematic component of zero offset voltage and high voltage gain within the combined GaAs process, which enables to use only nJFet field and p-n-p bipolar transistors.

3 cl, 5 dwg

Description

The proposed invention relates to the field of radio engineering and can be used as a basic analog unit for many automation devices, computer technology, communication systems and instrument making, incl. working at high temperatures.

In modern microelectronics, operational amplifiers (op-amps) have become widespread, which include an input differential stage on field-effect (or bipolar) transistors with a reference current source in a common source (emitter) circuit and an intermediate stage made on the basis of a so-called “bent” cascode circuit [ 1-54]. Operational amplifiers of this class have a wide range of operating frequencies, and when using JFet input transistors, they have an extremely low noise level. In addition, they use the supply voltage efficiently. The proposed invention relates to this class of op-amps.

In practical op-amp circuits, the input differential stage is implemented using both bipolar and field-effect transistors, which is determined by the technological processes used. However, the promising gallium arsenide technical process [55,56], mastered by the Minsk Research Institute of Radio Materials (https://mniirm.by/) and a number of foreign companies, ensures the creation of only nJFet field-effect and pnp bipolar transistors. The absence of n-p-n transistors creates circuit design problems for GaAs op-amps. This does not allow the creation of high-temperature GaAs op-amps, as well as high-temperature op-amps based on other wide-gap semiconductors (SiC, GaN, etc.) with a similar combination of available active elements, which are in demand in a number of important branches of science and technology - space instrument making, oil and gas, automotive and aviation industries.

The closest prototype (Fig. 1) of the proposed device is the operational amplifier presented in the publication “Bob Cordell. LSK489 Application Note. Low Noise Dual Monolithic JFET. URL: https://www.cordellaudio.com/JFETs/LSK489appnote.pdf. 16 p., fig. 10". This op-amp circuit is also presented in US patent 4.406.990, fig. 6 1983 The op-amp prototype contains the first 1 and second 2 inputs, as well as a potential output 3 of the device, an input differential stage 4 with the first 5 and second 6 current outputs, the common current input of which 7 is connected to the first 8 bus to establish the static mode of the transistors power source through the first 9 reference current source, the first 10 output transistor of the intermediate stage, the emitter of which is connected to the first 5 current output of the input differential stage 4 and through the first 11 current stabilizing resistor connected to the second 12 bus of the power source, the second 13 output transistor of the intermediate stage, emitter which is connected to the second 6 current output of the input differential stage 4 and through the second 14 current stabilizing resistor is connected to the second 12 power supply bus, and the base of the first 10 output transistor of the intermediate stage is connected to the base of the second 13 output transistor of the intermediate stage, current mirror 15 of the intermediate stage, output transistor 16, the emitter of which is connected to the output of device 3 and through the second 17 reference current source is connected to the second 12 bus of the power source, and the collector is connected to the first 8 bus of the power source.

A significant drawback of the prototype op-amp is that it is not implemented within the gallium arsenide technological process [55,56] due to the lack of npn gallium arsenide bipolar transistors. In addition, the known op-amp is characterized by an increased level of the systematic component of the zero bias voltage (U _cm ), which is due to the circuit used in it to establish a static mode on the bases of the first 10 and second 13 output bipolar transistors of the intermediate stage.

The main objective of the proposed invention is to create a precision operational amplifier circuit with a low level of the systematic component of the zero offset voltage and increased voltage gain within the framework of a combined GaAs technological process, allowing the use of only nJFet field-effect and pnp bipolar transistors.

The objectives are achieved by the fact that in the operational amplifier of FIG. 1, containing the first 1 and second 2 inputs, as well as the potential output 3 of the device, an input differential stage 4 with the first 5 and second 6 current outputs, the common current input of which 7 to establish the static mode of the transistors is connected to the first 8 power supply bus through the first 9 reference current source, the first 10 output transistor of the intermediate stage, the emitter of which is connected to the first 5 current output of the input differential stage 4 and through the first 11 current stabilizing resistor is connected to the second 12 power supply bus, the second 13 output transistor of the intermediate stage, the emitter of which is connected to the second 6 the current output of the input differential stage 4 and through the second 14 current-stabilizing resistor is connected to the second 12 bus of the power source, and the base of the first 10 output transistor of the intermediate stage is connected to the base of the second 13 output transistor of the intermediate stage, the current mirror 15 of the intermediate stage, the output transistor 16, the emitter of which connected to the output of device 3 and through the second 17 reference current source is connected to the second 12 bus of the power source, and the collector is connected to the first 8 bus of the power source, new elements and connections between them are provided - the first 18 and second 19 additional bipolar transistors are introduced into the circuit, the combined emitters of which are connected to the gate of the additional field-effect transistor 20 and, through an additional resistor 21, are connected to the combined bases of the first 10 and second 13 output transistors of the intermediate stage, which are connected to the source of the additional field-effect transistor 20, the drain of the additional field-effect transistor 20 is connected to the second 12 power supply bus , the base of the first 18 additional bipolar transistor is connected to the collector of the first 10 output transistor of the intermediate stage and through the third 22 reference current source is connected to the first 8 power supply bus, the base of the second 19 additional bipolar transistor is connected to the collector of the second 13 output transistor of the intermediate stage and through the fourth 23 the reference current source is connected to the first 8 bus of the power supply, the collector of the first 18 additional bipolar transistor is connected to the first 8 bus of the power source through the fifth 24 reference current source and is connected to the input of the current mirror 15 of the intermediate stage, the non-inverting output of which is connected to the output 3 of the device, and the inverting output is connected to the collector of the second 19 additional bipolar transistor and the base of the output transistor 16 and through the sixth 25 reference current source is connected to the first 8 power supply bus.

In the drawing FIG. Figure 1 shows the circuit of the prototype operational amplifier.

In the drawing FIG. Figure 2 shows a diagram of the proposed operational amplifier in accordance with claim 1 and claim 3 of the claims.

In the drawing FIG. 3 shows a diagram of the first 9, second 17, third 22, fourth 23, fifth 24, sixth 25 identical reference current sources on gallium arsenide field-effect transistors 26 and 27 and resistor 28, used in the op-amp of Fig. 2 in accordance with paragraph 2 and paragraph 3 of the claims

In the drawing FIG. 4 shows the static mode of the op amp Fig. 2 in the LTSpice environment on GaAs transistors at 27°C, reference current sources on field-effect transistors I1=I2=I3=I4=I5=I6=I7=200μA, R1=R2=R3=1kOhm.

In the drawing FIG. 5 The logarithmic amplitude-frequency characteristic of the op-amp voltage gain is presented in the drawing in Fig. 4.

Gallium Arsenide operational amplifier with increased gain and low systematic component of the zero offset voltage FIG. 2 contains the first 1 and second 2 inputs, as well as the potential output 3 of the device, an input differential stage 4 with the first 5 and second 6 current outputs, the common current input of which 7 to establish the static mode of the transistors is connected to the first 8 power supply bus through the first 9 source reference current, the first 10 output transistor of the intermediate stage, the emitter of which is connected to the first 5 current output of the input differential stage 4 and through the first 11 current stabilizing resistor is connected to the second 12 power supply bus, the second 13 output transistor of the intermediate stage, the emitter of which is connected to the second 6 current the output of the input differential stage 4 and through the second 14 current-stabilizing resistor is connected to the second 12 power supply bus, and the base of the first 10 output transistor of the intermediate stage is connected to the base of the second 13 output transistor of the intermediate stage, the current mirror 15 of the intermediate stage, the output transistor 16, the emitter of which is connected with the output of device 3 and through the second 17 reference current source is connected to the second 12 bus of the power source, and the collector is connected to the first 8 bus of the power source, characterized in that the first 18 and second 19 additional bipolar transistors are introduced into the circuit, the combined emitters of which are connected to the gate of the additional field-effect transistor 20 and through an additional resistor 21 are connected to the combined bases of the first 10 and second 13 output transistors of the intermediate stage, which are connected to the source of the additional field-effect transistor 20, the drain of the additional field-effect transistor 20 is connected to the second 12 power supply bus, the base of the first 18 additional bipolar transistor is connected to the collector of the first 10 output transistor of the intermediate stage and through the third 22 reference current source is connected to the first 8 power supply bus, the base of the second 19 additional bipolar transistor is connected to the collector of the second 13 output transistor of the intermediate stage and through the fourth 23 reference current source is connected to the first 8 bus of the power supply, the collector of the first 18 additional bipolar transistor is connected to the first 8 bus of the power source through the fifth 24 reference current source and is connected to the input of the current mirror 15 of the intermediate stage, the non-inverting output of which is connected to the output 3 of the device, and the inverting output is connected to the collector the second 19 additional bipolar transistor and the base of the output transistor 16 and through the sixth 25 reference current source is connected to the first 8 power supply bus.

In the drawings FIGS. 2 (in accordance with claim 2 of the claims) and FIG. 3 (in accordance with paragraph 3 of the claims), the first 9, second 17, third 22, fourth 23, fifth 24, sixth 25 reference current sources are made according to identical circuits based on cascode connection of field-effect transistors with a control p-n junction, each of which contains an output field-effect transistor 26, the gate of which is connected to the source of the matching field-effect transistor 27 and is connected to the first 8 bus of the power source through an auxiliary resistor 28, and the gate of the matching field-effect transistor 27 is connected to the source of the matching field-effect transistor 27 through an auxiliary resistor 28, and the drain of the matching field-effect transistor transistor 27 is connected to the source of the output field-effect transistor 26.

In addition, in the drawing of FIG. 2, in accordance with paragraph 3 of the claims, in parallel with the first 9 reference current source, an identical additional reference current source 29 is connected, made according to an identical circuit based on the cascode connection of field-effect transistors and containing an output field-effect transistor 26, the gate of which is connected to the source of the matching field-effect transistor 27 and connected to the first 8 bus of the power source through an auxiliary resistor 28, and the gate of the matching field-effect transistor 27 is connected to the source of the matching field-effect transistor 27 through the auxiliary resistor 28, and the drain of the matching field-effect transistor 27 is connected to the source of the output field-effect transistor 26.

In the drawing FIG. 2 current mirror 15 of the intermediate stage, made on transistors 30 and 31, has non-inverting 32 and inverting 33 current outputs.

Let us consider the operation of the proposed op-amp Fig. 2.

The proposed gallium arsenide op-amp circuit is characterized by an extremely low sensitivity of the zero bias voltage to the absolute values of the identical resistances of the used resistors 11, 14 and the numerical values of the current of the common current input 7, which sets the static mode of transistors 34 and 35 of the input differential stage 4. This effect has been confirmed computer modeling, is provided by an unconventional scheme for establishing a static mode on the bases of the first 10 and second 13 output transistors of the intermediate stage, which uses the first 18 and second 19 additional bipolar transistors, as well as an additional field-effect transistor 20.

Static mode of the op-amp circuit in the drawing of Fig. 2 is installed by reference current sources 9, 17, 22, 23, 24, 25, 29 on field-effect transistors with a control pn junction made according to the circuit of Fig.3. This is a fundamentally important condition for obtaining low levels of the systematic component of the zero offset voltage for the op-amp circuit of Fig. 2, because allows for mutual compensation of static currents in the high-impedance node Σ ₂ , at which the systematic component U _cm will be close to zero. Computer simulation fig. 4 shows that the systematic component of the zero offset voltage Ucm has a value of about 100 μV.

Thus, the claimed device is characterized by significant advantages in comparison with the op-amp prototype.

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Article on gallium arsenide chips

55. Unified circuit solutions for analog gallium arsenide microcircuits / Dvornikov O.V., Pavlyuchik A.A., Prokopenko N.N., Chekhovsky V.A., Kunz A.V., Chumakov V.E. // News of universities. Electronics. 2022. T. 27. No. 4. pp. 475–488. DOI: https://doi.org/10.24151/1561-5405-2022-27-4-475-488.

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Claims (3)

1. Gallium arsenide operational amplifier with increased gain and a low level of the systematic component of the zero offset voltage, containing the first (1) and second (2) inputs, as well as the potential output (3) of the device, an input differential stage (4) with the first ( 5) and the second (6) current outputs, the common current input of which (7) to establish the static mode of the transistors is connected to the first (8) power supply bus through the first (9) reference current source, the first (10) output transistor of the intermediate stage, the emitter which is connected to the first (5) current output of the input differential stage (4) and through the first (11) current stabilizing resistor is connected to the second (12) power supply bus, the second (13) output transistor of the intermediate stage, the emitter of which is connected to the second (6) current output of the input differential stage (4) and through the second (14) current stabilizing resistor is connected to the second (12) power supply bus, and the base of the first (10) output transistor of the intermediate stage is connected to the base of the second (13) output transistor of the intermediate stage, current mirror (15) intermediate stage, output transistor (16), the emitter of which is connected to the output of the device (3) and through the second (17) reference current source is connected to the second (12) power supply bus, and the collector is connected to the first (8) source bus power supply, characterized in that the first (18) and second (19) additional bipolar transistors are introduced into the circuit, the combined emitters of which are connected to the gate of the additional field-effect transistor (20) and through an additional resistor (21) are connected to the combined bases of the first (10) and the second (13) output transistors of the intermediate stage, which are connected to the source of the additional field-effect transistor (20), the drain of the additional field-effect transistor (20) is connected to the second (12) power supply bus, the base of the first (18) additional bipolar transistor is connected to the collector of the first ( 10) output transistor of the intermediate stage and through the third (22) reference current source is connected to the first (8) power supply bus, the base of the second (19) additional bipolar transistor is connected to the collector of the second (13) output transistor of the intermediate stage and through the fourth (23) the reference current source is connected to the first (8) power supply bus, the collector of the first (18) additional bipolar transistor is connected to the first (8) power supply bus through the fifth (24) reference current source and is connected to the input of the current mirror (15) of the intermediate stage, the non-inverting output of which is connected to the output (3) of the device, and the inverting output is connected to the collector of the second (19) additional bipolar transistor and the base of the output transistor (16) and through the sixth (25) reference current source is connected to the first (8) power supply bus. 2. A gallium arsenide operational amplifier with an increased gain and a low level of the systematic component of the zero offset voltage according to claim 1, characterized in that the first (9), second (17), third (22), fourth (23), fifth ( 24), the sixth (25) reference current sources are made according to identical circuits based on cascode connection of field-effect transistors with a control p-n junction, each of which contains an output field-effect transistor (26), the gate of which is connected to the source of the matching field-effect transistor (27) and connected to the first (8) power supply bus through an auxiliary resistor (28), and the gate of the matching field-effect transistor (27) is connected to the source of the matching field-effect transistor (27) through the auxiliary resistor (28), and the drain of the matching field-effect transistor (27) is connected to the source of the output field effect transistor (26). 3. A gallium arsenide operational amplifier with an increased gain and a low level of the systematic component of the zero offset voltage according to claim 1, characterized in that in parallel with the first (9) reference current source an additional reference current source (29) identical to it is connected, made in an identical way its circuit based on cascode connection of field-effect transistors and containing an output field-effect transistor (26), the gate of which is connected to the source of the matching field-effect transistor (27) and connected to the first (8) bus of the power source through an auxiliary resistor (28), and the gate of the matching field-effect transistor (27) is connected to the source of the matching field-effect transistor (27) through an auxiliary resistor (28), and the drain of the matching field-effect transistor (27) is connected to the source of the output field-effect transistor (26).