RU2786941C1 - Differential cascade on complementary field-effect transistors - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: differential cascade on complementary field-effect transistors is proposed, which contains the first (1) and second (2) inputs, the first (3) and second (4) current outputs aligned with the first (5) bus of the power supply, the first (6) input field-effect transistor, the second (7) bus of the power supply, first (8) auxiliary resistor, second (9) input field-effect transistor, second (10) auxiliary resistor, first (11) output field-effect transistor, second (12) output field-effect transistor, first (13) additional field-effect transistor, second (14) additional field-effect transistor.

EFFECT: invention enables to increase the steepness of the conversion of the input differential voltage into the output differential currents of the device, increasing the voltage gain.

3 cl, 11 dwg

Description

The invention relates to the field of radio engineering and can be used as a low-noise device for amplifying analog signals, in the structure of analog microcircuits for various functional purposes, for example, in operational amplifiers (op-amps), comparators, etc., incl. operating in a wide range of temperatures and exposure to radiation.

Known schemes of classical differential cascades (DC) on field effect transistors with a control p-n junction (JFet) [1-15], which became the basis of many low-noise analog microcircuits.

The closest prototype (Fig. 1) of the claimed device is a differential cascade presented in patent RU 2679970, fig. 2, 2019, which contains the first 1 and second 2 inputs, the first 3 and second 4 current outputs, matched with the first 5 power supply bus, the first 6 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the drain is matched with the second 7 power supply bus, the source is connected to the first terminal of the first 8 auxiliary resistor, the second 9 input field effect transistor, the gate of which is connected to the second 2 input of the device, the drain is matched with the second 7 power supply bus, the source is connected to the first terminal of the second 10 auxiliary resistor, the first 11 output field effect transistor, the drain of which is connected to the first 3 current output of the device, the second 12 output field effect transistor, the drain of which is connected to the second 4 current output of the device.

A significant drawback of the known DC of FIG. 1 is that when field-effect transistors operate in micromode, its gain slope (S _DC ) turns out to be small. This adversely affects the operation of micropower devices, such as operational amplifiers, comparators, in which the DC figure 1 is used in the input or intermediate stages.

The main objective of the proposed invention is to create conditions under which in the DC of Fig. 2 increases the steepness of the conversion of the input differential voltage into the output differential currents of the device (S _DC ), which is important when operating DC with low static currents of transistors, incl. gallium arsenide field-effect transistors [16]. Ultimately, this increases the voltage gain of practical DC switching circuits, for example, in operational amplifiers or voltage comparators.

The problem is solved by the fact that in the differential cascade of Fig. 1, containing the first 1 and second 2 inputs, the first 3 and second 4 current outputs, matched with the first 5 power supply bus, the first 6 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the drain is matched with the second 7 power supply bus, the source is connected to the first terminal of the first 8 auxiliary resistor, the second 9 input field-effect transistor, the gate of which is connected to the second 2 input of the device, the drain is connected to the second 7 power supply bus, the source is connected to the first terminal of the second 10 auxiliary resistor, the first 11 output field-effect transistor, the drain of which is connected to the first 3 current output of the device, the second 12 output field-effect transistor, the drain of which is connected to the second 4 current output of the device, new elements and connections are provided - the source of the first 6 input field-effect transistor is connected to the gate of the first 13 additional field-effect transistor, the source of which is connected with the source of the first 6 input field effect transistor through the first th 8 auxiliary resistor and is connected to the gate of the first 11 output FET, the drain of the first 13 additional FET is connected to the source of the first 11 output FET, the source of the second 9 input FET is connected to the gate of the second 14 additional FET, the source of which is connected to the source of the second 9 of the input FET through the second 10 auxiliary resistor and connected to the gate of the second 12 output FET, the drain of the second 14 additional FET is connected to the source of the second 12 output FET and is connected to the drain of the first 13 additional FET.

In the drawing of FIG. 1 shows a diagram of a DC prototype according to patent RU 2679970, fig. 2, 2019

In the drawing of FIG. 2 shows a diagram of the proposed differential stage in accordance with paragraph 1 and paragraph 2 of the claims for the case when complementary field-effect transistors with a control p-n junction are used as field-effect transistors.

In the drawing of FIG. 3 shows a diagram of the proposed differential stage in accordance with claim 3 of the claims for the case when complementary CMOS transistors with built-in p and n channels are used as field-effect transistors.

In the drawing of FIG. 4 shows the static mode in the LTSpice environment of the prototype differential stage of FIG. 1 at 27°С, resistors R1=R2=50kΩ, R4=R5=500kΩ. The choice of the numerical value of the resistances R4=R5=500 kOhm was made to exclude their influence on the steepness of the DC.

In the drawing of FIG. 5 shows the dependence of the output currents of the DC prototype of FIG. 4 from the input voltage at a temperature of 27°C and resistors R1=R2=50 kOhm, from which it follows that the DC - the prototype with the selected resistances of the resistors has a gain slope
S _dk ≈ 8.8 μA / V.

In the drawing of FIG. 6 shows the output currents of the DC prototype of FIG. 4 from the input voltage at negative temperatures (-197°С) and resistors R1=R2=50kΩ. Here S _dk ≈ 8.52 μA / V, i.e. the scheme under consideration is characterized by a weak dependence of S _dk on temperature.

In the drawing of FIG. 7 shows the static mode in the LTSpice environment of the inventive differential stage of FIG. 2 at 27°С, resistors R1=R2=50kΩ.

In the drawing of FIG. 8 shows the dependence of the output currents of the claimed DC of FIG. 7 from the input voltage at a temperature of 27°C and resistors R1=R2=50 kOhm, from which it follows that the slope of the DC amplification S _DC ≈ 150 μA/V.

In the drawing of FIG. 9 shows the dependence of the output currents of the claimed DC of FIG. 7 from the input voltage at negative temperatures (-197°С) and resistors R1=R2=50kΩ. In this mode, S _dk ≈ 100 μA/V.

In the drawing of FIG. 10 shows a diagram of an input differential stage with a gain multiplier (Fig. 2) for the case when JFETs with a p-channel are used as the first 6 and second 9 input FETs.

In the drawing of FIG. 11 shows an application example of the differential input stage of FIG. 10 for the case where GaAs p-n-p bipolar transistors are used as the first 6 and second 9 input transistors.

The differential cascade on complementary field-effect transistors of Fig. 2 contains the first 1 and second 2 inputs, the first 3 and second 4 current outputs, matched with the first 5 power supply bus, the first 6 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the drain is matched with the second 7 power supply bus, the source connected to the first output of the first 8 auxiliary resistor, the second 9 input field effect transistor, the gate of which is connected to the second 2 input of the device, the drain is matched with the second 7 power supply bus, the source is connected to the first output of the second 10 auxiliary resistor, the first 11 output field effect transistor, drain which is connected to the first 3 current output of the device, the second 12 output field-effect transistor, the drain of which is connected to the second 4 current output of the device. The source of the first 6 input field effect transistor is connected to the gate of the first 13 additional field effect transistor, the source of which is connected to the source of the first 6 input field effect transistor through the first 8 auxiliary resistor and is connected to the gate of the first 11 output field effect transistor, the drain of the first 13 additional field effect transistor is connected to the source of the first 11 output field-effect transistor, the source of the second 9 input field-effect transistor is connected to the gate of the second 14 additional field-effect transistor, the source of which is connected to the source of the second 9 input field-effect transistor through the second 10 auxiliary resistor and is connected to the gate of the second 12 output field-effect transistor, the drain of the second 14 additional field-effect transistor transistor is connected to the source of the second 12 output FET and is connected to the drain of the first 13 additional FET. In the diagram of Fig. 2 two-terminal networks R _n1 and R _n2 simulate the properties of the load.

In the drawing of FIG. 2, in accordance with paragraph 2 of the claims, field-effect transistors with a control p-n junction are used as complementary field-effect transistors.

In the drawing of FIG. 3, in accordance with paragraph 3 of the claims, CMOS transistors with built-in p and n channels are used as complementary field-effect transistors [17].

Let us consider the operation of the DC of Fig. 2.

In static mode, for example, when connecting the first 1 and second 2 inputs of DC Fig. 2 to a common power supply bus, the static currents of the sources of the first 6 and second 9 input field-effect transistors, the first 11 and second 12 output field-effect transistors, the first 13 and second 14 additional field-effect transistors are determined by the numerical values of the identical resistances of the first 8 and second 10 auxiliary resistors:

, (1)

, (one)

where I _ii is the source current of the i-th field-effect transistor (6, 9, 11, 12, 13, 14);

U _zi.i - gate-source voltage of the first 13 and second 14 additional field-effect transistors at the operating point at the source current equal to the specified value I ₀ , for example, 200 μA;

R _i are the resistances of the first 8 and second 10 auxiliary resistors.

Thus, in the diagram of Fig. 2 due to the choice of identical resistances of the first 8 and second 10 auxiliary resistors with known drain-gate characteristics of identical JFETs, a given static current mode is provided, incl. given constant voltage at the sources of the first 11 and second 12 output field-effect transistors: U _s.11 =U _s.12 =U _zi.6 -U _zi.13 -U _zi.11 .

If a positive increment of the input voltage u _in relative to input 2 is applied to input 1, then this causes an increase in the voltage at the source of the first 6 input field-effect transistor (u _s.6 ), the gate of the first 13 additional field-effect transistor, the source of the first 13 additional field-effect transistor (u _{s .13} ) and the gate of the first 11 output field effect transistor u _s.13 , moreover:

u _s.6 =u _s.13 ≈ u _s.11 ≈u _in . (2)

The voltage increment at the gate of the first 11 output FET u _g.11 =u _s.13 causes a decrease in the drain current of this FET:

, (3)

, (3)

where S ₁₁ \u003d S ₁₂ is the steepness of the drain-gate characteristics of the first 11 and second 12 field-effect output transistors.

Therefore, the signal at the output _{Vy.i 1} (3) is inverted relative to the signal u in at the input 1 of the device. In this case, the increment of current i _s.11 ⁽⁺⁾ is transferred to the source circuit of the second 12 output field-effect transistor. Therefore, the voltage at the second 4 current output of the device is in phase with the voltage u _in at the input 1 of the differential stage.

In particular cases, CMOS transistors with a built-in channel can be used as field-effect transistors (Fig. 3). In this case, the CMOS DC of FIG. 3, as well as JFet DC figure 2, has an increased gain slope of the differential signal. This circuit solution is promising for the construction of operational amplifiers implemented using CMOS transistors with a built-in channel [17].

In the DC scheme in the drawing of Fig. 10, corresponding to claim 1 of the claims, as the first 6 and second 9 input field-effect transistors, p-channel JFETs are used.

It should be noted that when using combined GaAs technological processes, the first 6 and second 9 input transistors can be made as GaAs p-n-p bipolar transistors (see Fig. 11).

Thus, the claimed DC has significant advantages in terms of gain slope in comparison with the DC prototype, which allows us to recommend it for practical use in analog circuits containing, for example, field-effect transistors, incl. CMOS transistors with built-in channel.

REFERENCES

1. Patent RU 2710296, 2019

2. Auto light USSR 537435, 1976

3. Patent application RU 2020134402, 2020

4. Patent US 5.291.149, fig. 3, 1994

5. Patent RU 2679970, fig. 2, 2019

6. Patent RU 2624565, fig. 1, 2016

7. Patent RU 2571399, fig. 2, 2014

8. Auto. USSR 437193, 1972

9. Patent application US 2006/01255222, 2006

10. Patent US 4.121.169, fig. 5, fig. 6, 1978

11. Patent US 9.668.045, 2017

12. Patent US 9.888.315, 2018

13. Patent US 9.167.327, 2015

14. Patent EP 0293488, fig. 1, 1988

15. Patent US 5.166.553, fig. 14, 1992

16. Shur, Michael S., “GaAs Devices and Circuits,” Springer Science+Business Media, New York, 1987, 677 p. DOI 10.1007/978-1-4899-1989-2

17. Sanchez-Sinencio Edgar, Allen Phillip "Electronic Circuits with Switched Capacitors", Radio and Communication Publishing House, 1989, p. 548, fig. 8.7.9.

Claims (3)

1. Differential stage on complementary field-effect transistors, containing the first (1) and second (2) inputs, the first (3) and second (4) current outputs, matched with the first (5) power supply bus, the first (6) input field-effect transistor , the gate of which is connected to the first (1) input of the device, the drain is matched to the second (7) power supply bus, the source is connected to the first output of the first (8) auxiliary resistor, the second (9) input field-effect transistor, the gate of which is connected to the second (2 ) device input, the drain is matched with the second (7) power supply bus, the source is connected to the first output of the second (10) auxiliary resistor, the first (11) output field-effect transistor, the drain of which is connected to the first (3) current output of the device, the second (12 ) output field-effect transistor, the drain of which is connected to the second (4) current output of the device, characterized in that the source of the first (6) input field-effect transistor is connected to the gate of the first (13) additional field-effect transistor ra, the source of which is connected to the source of the first (6) input field-effect transistor through the first (8) auxiliary resistor and is connected to the gate of the first (11) output field-effect transistor, the drain of the first (13) additional field-effect transistor is connected to the source of the first (11) output field-effect transistor transistor, the source of the second (9) input field-effect transistor is connected to the gate of the second (14) additional field-effect transistor, the source of which is connected to the source of the second (9) input field-effect transistor through the second (10) auxiliary resistor and is connected to the gate of the second (12) output field-effect transistor transistor, the drain of the second (14) additional field effect transistor is connected to the source of the second (12) output field effect transistor and is connected to the drain of the first (13) additional field effect transistor. 2. Differential cascade on complementary field-effect transistors according to claim 1, characterized in that field-effect transistors with a control p-n junction are used as complementary field-effect transistors. 3. Differential cascade on complementary field-effect transistors according to claim 1, characterized in that CMOS transistors with built-in p and n channels are used as complementary field-effect transistors.

Images