RU2780220C1 - Operational amplifier based on two-stroke "inverse" cascode and complementary fet-steristors with control pn-junction - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention relates to the field of radio engineering. To achieve the effect, an operational amplifier based on a push-pull "kinked" cascode and complementary field-effect transistors with a control pn-junction is proposed, in which the source of the first (4) input field-effect transistor is connected to the gate of the third (6) input field-effect transistor and through the first (16) auxiliary resistor connected to the source of the third (6) input FET, the source of the second (5) input FET is connected to the gate of the fourth (7) input FET and through the second (17) auxiliary resistor is connected to the combined sources of the first (6) and second (7) input field effect transistors.

EFFECT: creation of conditions under which the input capacitance in the op-amp is halved, and small values of the systematic component of the zero bias voltage are realized.

4 cl, 7 dwg

Description

The invention relates to the field of radio engineering and can be used as a low-noise device for amplifying analog signals, in the structure of analog interfaces for various functional purposes, incl. operating in a wide range of temperatures and exposure to radiation.

There are circuits of classical operational amplifiers (op-amps) containing the so-called push-pull "kinked" cascode, which includes two "kinked" cascodes on field-effect transistors with p and n channels, loaded on each other and having a common high-impedance node [1-11]. This is one of the most popular op-amp circuits in analog microelectronics. At the same time, the input stages of such op-amps are performed within dozens of different circuit solutions [1-11].

The closest prototype (Fig. 1) of the proposed device is an operational amplifier based on a push-pull "kinked" cascode, presented in the article by Dimitri Danyuk "Linear Integrated Systems Headphone Amplifier Evaluation Board", Linear Integrated Systems, p. 1-17, URL: http://www.linearsystems.com/lsdata/others/Headphone_Amplifier_Evaluation_Board.pdf. It contains the first 1 and second 2 inputs of the device, the current output 3 of the device, the first 4, the second 5, the third 6 and the fourth 7 input field-effect transistors, the first 8 output field-effect transistor, the gate of which is connected to the first 9 bias voltage source, the drain is connected to the current output 3 of the device, and the source is connected to the drain of the second 5 input field-effect transistor and through the first 10 current-stabilizing two-pole is connected to the first 11 power supply bus, the second 12 output field-effect transistor, the gate of which is connected to the second 13 bias voltage source, the drain is connected to the current output 3 device, and the source is connected to the drain of the fourth 7 input field-effect transistor and through the second 14 current-stabilizing two-pole is connected to the second 15 power supply bus, the gate of the first 4 input field-effect transistor is connected to the first 1 input of the device, and its drain is matched to the first 11 power supply bus, the gate of the second 5 input field effect transistor is connected to the second 2 input device, the drain of the third 6 input field-effect transistor is matched with the second 15 power supply bus, the first 16 and second 17 are auxiliary resistors.

A significant drawback of the known op-amp of Fig. 1 is that it has an increased input capacitance, which adversely affects the operation of the circuit in the high frequency range. In addition, it does not provide small values of the systematic component of the zero bias voltage (Ucm), which is due to the shortcomings of its architecture.

The main objective of the proposed invention is to create conditions under which the input capacitance in the op-amp is halved (due to this, an extended operating frequency range is provided), and small values of the systematic component of the zero bias voltage (Ucm) are realized, which is determined by the symmetry and quality of the circuit design. solution of the CO in its "ideal" construction, and in this case is close to zero. In this case, the positive effect in the scheme of Fig. 2 is provided due to the special construction of the input differential stage of the op-amp and the push-pull "bent" cascode in accordance with the claims.

The problem is solved by the fact that in the OS of Fig. 1, containing the first 1 and second 2 inputs of the device, the current output 3 of the device, the first 4, the second 5, the third 6 and the fourth 7 input field-effect transistors, the first 8 output field-effect transistor, the gate of which is connected to the first 9 bias voltage source, the drain is connected to current output 3 of the device, and the source is connected to the drain of the second 5 input field-effect transistor and through the first 10 current-stabilizing bipolar connected to the first 11 power supply bus, the second 12 output field-effect transistor, the gate of which is connected to the second 13 bias voltage source, the drain is connected to the current output 3 devices, and the source is connected to the drain of the fourth 7 input field-effect transistor and through the second 14 current-stabilizing bipolar is connected to the second 15 power supply bus, the gate of the first 4 input field-effect transistor is connected to the first 1 input of the device, and its drain is matched to the first 11 power supply bus , the gate of the second 5 input FET is connected to the second 2 device input, the drain of the third 6 input field-effect transistor is matched with the second 15 power supply bus, the first 16 and second 17 auxiliary resistors, new elements and connections are provided - the source of the first 4 input field-effect transistor is connected to the gate of the third 6 input field-effect transistor and through the first 16 auxiliary the resistor is connected to the source of the third 6 input field-effect transistor, the source of the second 5 input field-effect transistor is connected to the gate of the fourth 7 input field-effect transistor, and through the second 17 auxiliary resistor is connected to the combined sources of the first 6 and second 7 input field-effect transistors, the first current-stabilizing bipolar 10 contains the first 18 and second 19 additional field-effect transistors, the gates of which are connected to the first 11 power supply bus, the drains are combined and connected to the source of the second 8 output field-effect transistor, and the source of the first 18 additional field-effect transistor is connected to the first 11 source bus and power supply through the first 20 additional resistor, and the source of the second 19 additional field-effect transistor is connected to the first 11 power supply bus through the second 21 additional resistor, the second 14 current-stabilizing two-pole contains the third 22 and 23 fourth additional field-effect transistors, the gates of which are connected to the source of the second 12 output field effect transistor, the drains are combined and connected to the second 15 power supply bus, and the source of the third 22 additional field effect transistor is connected to the source of the second 12 output field effect transistor through the third 24 additional resistor, and the source of the fourth 23 additional field effect transistor is connected to the source of the second 12 output field effect transistor through the fourth 25 additional resistor.

In the drawing of FIG. 1 shows a diagram of the op-amp prototype, and the drawing of FIG. 2 shows a diagram of the claimed device in accordance with paragraph 1, paragraph 2 and paragraph 3 of the claims.

In the drawing of FIG. 3 shows a diagram of the claimed device in accordance with paragraph 4 of the claims.

In the drawing of FIG. 4 shows a circuit for simulating the operational amplifier of FIG. 2 in the LTspice environment on models of Si field-effect transistors of OAO Integral (Minsk) at room temperature t=27^°C, R_one÷R₆\u003d 10.2 kOhm (R₁₆=R₁₇=R_twenty=R₂₁=R₂₄=R₂₅, see fig. 2), voltages on the first 28 and second 29 auxiliary two-terminal devices 4 V, voltage of the first 9 bias voltage source 5.3 V, voltage of the second (13) bias voltage source -4 V, capacitance of the correction capacitor (30) - 15 pF, voltages on the first 11 and second 15 power supply buses ±10 V.

In the drawing of FIG. 5 shows the logarithmic frequency response (LAFC) of the OA of FIG. 4 at room temperature t = 27°C.

In the drawing of FIG. Figure 6 shows a circuit for modeling the operational amplifier of Figure 2 at cryogenic temperatures (t = -197°C), R1÷R6=10 kOhm (R16=R17=R20=R21=R24=R25, see Figure 2), voltage of the first 9 bias voltage source 5 V, the voltage of the second bias voltage source 13 is -4.51 V, the capacitance of the correction capacitor (30) is 10 pF on models of Si field-effect transistors of OAO Integral (Minsk).

In the drawing of FIG. 7 shows the LAFC OU of FIG. 6 at cryogenic temperatures (t = -197 ^° C).

An operational amplifier based on a push-pull "bent" cascode and complementary field-effect transistors with a control pn-junction Fig. 2 contains the first 1 and second 2 inputs of the device, the current output 3 of the device, the first 4, the second 5, the third 6 and the fourth 7 input field-effect transistors, the first 8 output field-effect transistor, the gate of which is connected to the first 9 bias voltage source, the drain is connected to the current output 3 of the device, and the source is connected to the drain of the second 5 input field-effect transistor and through the first 10 current-stabilizing two-pole is connected to the first 11 power supply bus, the second 12 output field-effect transistor, the gate of which is connected to the second 13 bias voltage source, the drain is connected to the current output 3 device, and the source is connected to the drain of the fourth 7 input field-effect transistor and through the second 14 current-stabilizing two-pole is connected to the second 15 power supply bus, the gate of the first 4 input field-effect transistor is connected to the first 1 input of the device, and its drain is matched to the first 11 power supply bus, the gate of the second 5 input field effect transistor is connected to the second 2 input house of the device, the drain of the third 6 input field-effect transistor is matched with the second 15 power supply bus, the first 16 and second 17 auxiliary resistors. The source of the first 4 input field-effect transistor is connected to the gate of the third 6 input field-effect transistor and through the first 16 auxiliary resistor is connected to the source of the third 6 input field-effect transistor, the source of the second 5 input field-effect transistor is connected to the gate of the fourth 7 input field-effect transistor, and through the second 17 auxiliary resistor connected to the combined sources of the first 6 and second 7 input field-effect transistors, the first current-stabilizing bipolar 10 contains the first 18 and second 19 additional field-effect transistors, the gates of which are connected to the first 11 power supply bus, the drains are combined and connected to the source of the second 8 output field-effect transistor, and the source of the first 18 additional field-effect transistor is connected to the first 11 power supply bus through the first 20 additional resistor, and the source of the second 19 additional field-effect transistor is connected to the first 11 power supply bus through the second 21 additional resistor, the second 14 current-stabilizing two-terminal contains the third 22 and fourth 23 additional field-effect transistors, the gates of which are connected to the source of the second 12 output field-effect transistor, the drains are combined and connected to the second 15 power supply bus, and the source of the third 22 additional field-effect transistor is connected to the source of the second 12 output field-effect transistor through the third 24 additional resistor, and the source of the fourth 23 additional field effect transistor is connected to the source of the second 12 output field effect transistor through the fourth 25 additional resistor.

In the drawing of FIG. 2, in accordance with paragraph 2 of the claims, the current output 3 of the device is connected to the input of the buffer amplifier 26, the output of which 27 is the potential output of the device.

In addition, in the drawing of FIG. 2, in accordance with paragraph 3 of the claims, the drain of the first 4 input field-effect transistor is matched with the first 11 power supply bus through the first 28 auxiliary two-pole, and the drain of the third 6 input field-effect transistor is matched with the second 15 power supply bus through the second 29 auxiliary two-pole.

In the drawing of FIG. 3, in accordance with paragraph 4 of the claims, the first 4, second 5, third 6 and fourth 7 input field-effect transistors, as well as the first 8 and second 12 output field-effect transistors, are made as cascode compound transistors according to classical circuits (4.1, 4.2) , (5.1, 5.2), (6.1, 6.2), (7.1, 7.2), (8.1, 8.2) (12.1, 12.2).

The stability of the OS of Fig. 2 and FIG. 3 is provided by a correction capacitor 30.

Consider the operation of the op-amp of Fig. 2.

In static mode, for example, when connecting the first 1 and second 2 inputs of the OS of Fig. 2 to a common power supply bus, the static currents of the sources of the first 4, second 5, third 6 and fourth 7 input field-effect transistors, as well as the first 18, second 19 and third 22 additional field-effect transistors are determined by the numerical values of the identical resistances of the first 16 and second 17 auxiliary resistors , as well as the first 20, second 21, third 24 and fourth 25 additional resistors:

, (1)

, (one)

where I _ii is the source current of the i-th field-effect transistor;

U _z.i - gate-source voltage of the corresponding field-effect transistors at the operating point at a source current equal to I ₀ ;

R _i - identical resistances of the corresponding auxiliary and additional resistors (18, 19, 22, 16, 17, 20, 21, 24, 25).

Thus, in the diagram of Fig. 2 by choosing the same resistances of the first 16 and second 17 auxiliary resistors, the first 20, the second 21, the third 24 and the fourth 25 additional resistors with identical drain-gate characteristics of the third 6 and fourth 7 input field-effect transistors, the first 18, the second 19 and the third 22 and the fourth 23 additional field-effect transistors provide an identical static mode for the drain current. This is a necessary condition for minimizing the systematic component of the zero bias voltage Ucm of the operational amplifier, since in this case the current error in the high-impedance node 3 (ΔI ₃ ) is close to zero:

(2)

(2)

where S _Σ is the gain slope of the op-amp from the inputs 1 and 2 of the device to the current output 3.

This conclusion is confirmed by the results of computer simulation in the drawings of Fig.4 and Fig.6, from which it follows that the systematic component of the zero bias voltage (without taking into account the spread of the parameters of the elements) is 26.8 μV (at t = 27 degrees), and 1.9 μV (at t = -197 degrees). This effect is provided due to the special construction of the scheme of the proposed OS.

The expansion of the frequency of the claimed op amp is due to the fact that the gate of only one field effect transistor 4 (5) is connected to the inputs 1 (2) of the device, i.e. the equivalent input capacitance in the proposed op-amp circuit is two times less than in the op-amp circuit of the prototype of Fig.1.

Thus, the claimed device has significant advantages in comparison with the op-amp prototype, which allows us to recommend it for practical use in analog interfaces containing, for example, field-effect transistors with a control pn-junction or CMOS transistors with a built-in channel, which have similar current-voltage performance compared to JFET.

REFERENCES

1. Patent US 2005/0128000, fig.1, 2005

2. Patent US 4.600.893, fig.3, 1986

3. Patent US 4.284.959, fig.3, 1981

4. Patent US 4783637, fig.2, 1988

5. Patent US 5.729.177, fig.1, 1988

6. Patent RU 2331966, fig.1, 2008

7. Patent RU 2517699, fig.1, 2012

8. Patent US 4.837.523, fig.4, 1989

9. Patent RU 2193273, fig.1, 2002

10. Patent US 3569848, fig.8, 1971

11. Enns V.I., Kobzev Yu.M. Design of analog CMOS microcircuits. Developer's Quick Reference Guide / Edited by Ph.D. tech. Sciences V. I. Enns. - M.: Hotline-Telecom. – 2005. – P. 207, fig. 3.81.

Claims (4)

1. Operational amplifier based on a push-pull "kinked" cascode and complementary field-effect transistors with a control pn-junction, containing the first (1) and second (2) inputs of the device, the current output (3) of the device, the first (4), the second (5) , third (6) and fourth (7) input field-effect transistors, the first (8) output field-effect transistor, the gate of which is connected to the first (9) source of bias voltage, the drain is connected to the current output (3) of the device, and the source is connected to the drain of the second (5) input field effect transistor and through the first (10) current-stabilizing two-terminal connected to the first (11) power supply bus, the second (12) output field effect transistor, the gate of which is connected to the second (13) bias voltage source, the drain is connected to the current output ( 3) device, and the source is connected to the drain of the fourth (7) input field-effect transistor and through the second (14) current-stabilizing two-pole connected to the second (15) power supply bus, the gate of the first (4) input field-effect transistor transistor is connected to the first (1) input of the device, and its drain is connected to the first (11) power supply bus, the gate of the second (5) input field-effect transistor is connected to the second (2) input of the device, the drain of the third (6) input field-effect transistor is matched with second (15) power supply bus, first (16) and second (17) auxiliary resistors, characterized in that the source of the first (4) input FET is connected to the gate of the third (6) input FET and through the first (16) auxiliary resistor is connected to the source of the third (6) input FET, the source of the second (5) input FET is connected to the gate of the fourth ( 7) input field effect transistor and through the second (17) auxiliary resistor is connected to the combined sources of the first (6) and second (7) input field effect transistors, the first current-stabilizing bipolar (10) contains the first (18) and second (19) additional field effect transistors, the gates of which are connected to the first (11) power supply bus, the drains are combined and connected to the source of the second (8) output field-effect transistor, and the source of the first (18) additional field-effect transistor is connected to the first (11) power supply bus through the first (20) additional resistor, and the source of the second (19) additional field effect transistor is connected to the first (11) power supply bus through the second (21) an additional resistor, the second (14) current-stabilizing two-pole contains the third (22) and fourth (23) additional field-effect transistors, the gates of which are connected to the source of the second (12) output field-effect transistor, the drains are combined and connected to the second (15) source bus supply, and the source of the third (22) additional field effect transistor is connected to the source of the second (12) output field effect transistor through the third (24) additional resistor, and the source of the fourth (23) additional field effect transistor is connected to the source of the second (12) output field effect transistor through the fourth (25) additional resistor. 2. An operational amplifier based on a push-pull "kinked" cascode and complementary field-effect transistors with a control pn-junction according to claim 1, characterized in that the current output (3) of the device is connected to the input of a buffer amplifier (26), the output of which (27) is potential output of the device. 3. An operational amplifier based on a push-pull "bent" cascode and complementary field-effect transistors with a control pn-junction according to claim 1, characterized in that the drain of the first (4) input field-effect transistor is connected to the first (11) power supply bus through the first (28 ) auxiliary two-pole, and the drain of the third (6) input field-effect transistor is connected to the second (15) power supply bus through the second (29) auxiliary two-terminal. 4. An operational amplifier based on a push-pull "bent" cascode and complementary field-effect transistors with a control pn-junction according to claim 1, characterized in that the first (4), second (5), third (6) and fourth (7) input field transistors, as well as the first 8 and second 12 output field-effect transistors are made as cascode composite transistors (4.1, 4.2), (5.1, 5.2), (6.1, 6.2), (7.1, 7.2), (8.1, 8.2) (12.1, 12.2 ).

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