RU2776031C1 - Current threshold element of left cyclic shift - Google Patents

Abstract

FIELD: radio engineering; analog microelectronics.

SUBSTANCE: invention relates to the field of radio engineering and analog microelectronics; it can be used in fast-acting analog and analog-digital interfaces for processing sensor signals.

EFFECT: creation of a current threshold element of the left cyclic shift, in which inner information conversion is performed in a current form of signals, which allows for an increase in performance of information conversion devices.

1 cl, 4 dwg, 1 tbl

Description

The present invention relates to the field of computer technology, automation, communications and can be used in various digital structures and systems for automatic control, transmission of digital information, etc.

In various computing and control systems, comparators implemented on the basis of emitter-coupled logic [1-15] are widely used, operating according to the laws of Boolean algebra and having two logical states “0” and “1” at the output, characterized by low and high potentials.

In the patent [16], articles [17-20], as well as monographs [21-22], it is shown that Boolean algebra is a special case of a more general linear algebra, the practical implementation of which in the structure of computational and logical automation devices of a new generation requires the creation of a special elemental base implemented on the basis of logic with a multi-valued internal representation of signals, in which the equivalent of a standard logic signal is the current quantum I ₀ . The claimed device "Current threshold element of the left cyclic shift" refers to this type of logic elements.

The closest prototype of the claimed device is a logic element presented in patent RU 2725149 (“Current threshold element of the right cyclic shift”, IPC H03K 19/17, 2020). It contains (Fig. 1) the first 1 and second 2 inputs of the device, the output 3 of the device, the first 4, the second 5, the third 6, the fourth 7, the fifth 8 and the sixth 9 input field-effect transistors with combined gates, which are connected to the first 10 voltage source bias, seventh 11, eighth 12, ninth 13, tenth 14, eleventh 15 and twelfth 16 input field-effect transistors of another type of conductivity with combined gates, which are connected to the second 17 bias voltage source, drains of the first 4, second 5, third 6, fifth 8 and the sixth 9 input field-effect transistors are connected to the first 18 power supply bus, the drains of the seventh 11, ninth 13 and tenth 14 input field-effect transistors are connected to the second 19 power supply bus, the thirteenth 20 and fourteenth 21 input field-effect transistors with combined gates, which are connected to the third 22 bias voltage source, the drains of the thirteenth 20 and fourteenth 21 input field-effect transistors are connected to the first 18 bus power supplies, the fifteenth 23 and sixteenth 24 input field-effect transistors of another type of conductivity with combined gates, which are connected to the fourth 25 bias voltage source, the drains of the fifteenth 23 and sixteenth 24 input field-effect transistors are connected to the second 19 power supply bus, the seventeenth 26 and eighteenth 27 input field-effect transistors, nineteenth 28, twentieth 29, twenty-first 30, twenty-second 31, twenty-third 32 and twenty-fourth 33 input field effect transistors of a different type of conductivity, the first 34 current mirror, matched with the first 18 power supply bus, containing the first 35, the second 36 , third 37, fourth 38 and fifth 39 outputs, the input of which is connected to the first 1 input of the device, the second 40 and third 41 current mirrors, matched with the first 18 power supply bus, fourth 42, fifth 43, sixth 44, seventh 45, eighth 46 and ninth 47 current mirrors, matched with the second bus 19 power supplies, tenth 48 current new mirror, matched with the first 18 power supply bus and containing the first 49 and second 50 outputs, the input of which is connected to the second 2 input of the device, the first 51, the second 52, the third 53, the fourth 54, the fifth 55, the sixth 56, the seventh 57, the eighth 58, ninth 59 and tenth 60 reference current sources, the first 35 output of the first 34 current mirror is connected to the combined sources of the first 4 and seventh 11 input field-effect transistors, the gate of the nineteenth 28 input field-effect transistor and is connected to the second 19 power supply bus through the first 51 reference source current, the drain of the nineteenth 28 input field-effect transistor is matched with the second 19 power supply bus, the sources of the nineteenth 28 and twentieth 29 input field-effect transistors are combined and connected to the first 18 power supply bus through the second 52 reference current source, the gate of the twentieth 29 input field-effect transistor is connected to the fifth 61 bias voltage source, drain of the twentieth 29 input field effect transistor the ora is connected to the input of the fourth 42 current mirror, the second 36 output of the first 34 current mirror is connected to the combined sources of the second 5 and eighth 12 input field-effect transistors, the output of the fourth 42 current mirror and is connected to the first 18 power supply bus through the third 53 reference current source, the third 37 the output of the first 34 current mirror is connected to the combined sources of the third 6 and ninth 13 input field-effect transistors, the gate of the seventeenth 26 input field-effect transistor and is connected to the second 19 power supply bus through the fourth 54 reference current source, the fourth 38 output of the first 34 current mirror is connected to the input fifth 43 current mirror, fifth 39 output of the first 34 current mirror is connected to the combined sources of the sixth 9 and twelfth 16 input field-effect transistors and connected to the output of the seventh 45 current mirror, the sources of the seventeenth 26 and eighteenth 27 input field-effect transistors are combined and connected to the second 19 source bus food i through the fifth 55 reference current source, the drain of the seventeenth 26 input field-effect transistor is connected to the first 18 power supply bus, the drain of the eighteenth 27 input field-effect transistor is matched with the input of the second 40 current mirror, the gate of the eighteenth 27 input field-effect transistor is connected to the sixth 62 bias voltage source, the output of the fifth 43 current mirror is connected to the combined sources of the fourth 7 and tenth 14 input field-effect transistors and is matched with the first 18 power supply bus through the sixth 56 reference current source, the drain of the fourth 7 input field-effect transistor is connected to the input of the third 41 current mirror, the outputs of the second 40 and the third 41 current mirrors are connected and connected to the combined sources of the fifth 8 and eleventh 15 input field-effect transistors, the drains of the eighth 12, eleventh 15 and twelfth 16 input field-effect transistors are combined and connected to the input of the sixth 44 current mirror, the output of which is matched with the output 3 of the device properties, the first 49 output of the tenth 48 current mirror is connected to the combined sources of the thirteenth 20 and fifteenth 23 input field-effect transistors, the gate of the twenty-first 30 input field-effect transistor and is connected to the second 19 power supply bus through the seventh 57 reference current source, the second 50 output of the eleventh 48 current the mirror is connected to the combined sources of the fourteenth 21 and sixteenth 24 input field-effect transistors, the gate of the twenty-third 32 input field-effect transistor and is connected to the second 19 power supply bus through the ninth 59 reference current source, the sources of the twenty-first 30 and twenty-second 31 input field-effect transistors are combined and matched with the first 18 power supply bus through the eighth 58 reference current source, the drain of the twenty-second 31 input field-effect transistor is connected to the input of the seventh 45 current mirror, the gate of the twenty-second 31 input field-effect transistor is connected to the seventh 63 bias voltage source, sources twenty-third 32 and twenty-fourth 33 input field-effect transistors are combined and connected to the first 18 power supply bus through the tenth 60 reference current source, the drain of the twenty-third 32 input field-effect transistor is connected to the input of the eighth 46 current mirror, the gate of the twenty-fourth 33 input field-effect transistor is connected to eighth 64 bias voltage source, the drains of the twenty-first 30 and twenty-fourth 33 input field-effect transistors are combined and connected to the input of the ninth 47 current mirror.

A significant drawback of the known logical element is that it does not implement the logical function of the left cyclic shift. This does not allow creating a complete basis of computer technology, operating on the principles of converting multivalued current signals. First of all, this is due to the fact that the known circuit has signal conversion errors that occur at each operation, these errors inevitably add up in the output signal and can lead to noticeable overall deviations from the levels of the reference signals. The use of threshold functions and their corresponding threshold elements, in addition to implementing a given logic function, ensures scaling and normalization of output signal levels and thereby eliminates all signal errors that occur before the threshold element.

The main objective of the proposed invention is to create a current threshold element of the left cyclic shift, in which the internal transformation of information is performed in the current form of signals. Ultimately, this makes it possible to increase performance and create an element base of computing devices operating on the principles of multivalued linear algebra [17–18].

The problem is solved by the fact that in the logical element (figure 1),

containing the first 1 and second 2 inputs of the device, the output 3 of the device, the first 4, the second 5, the third 6, the fourth 7, the fifth 8 and the sixth 9 input field-effect transistors with combined gates, which are connected to the first 10 bias voltage source, the seventh 11, the eighth 12, ninth 13, tenth 14, eleventh 15 and twelfth 16 input field-effect transistors of another type of conductivity with combined gates, which are connected to the second 17 bias voltage source, drains of the first 4, second 5, third 6, fifth 8 and sixth 9 input field-effect transistors connected to the first 18 power supply bus, the drains of the seventh 11, ninth 13 and tenth 14 input field-effect transistors are connected to the second 19 power supply bus, the thirteenth 20 and fourteenth 21 input field-effect transistors with combined gates, which are connected to the third 22 bias voltage source, drains thirteenth 20 and fourteenth 21 input field-effect transistors are connected to the first 18 power supply bus the fifteenth 23 and sixteenth 24 input field-effect transistors of another type of conductivity with combined gates, which are connected to the fourth 25 bias voltage source, the drains of the fifteenth 23 and sixteenth 24 input field-effect transistors are connected to the second 19 power supply bus, the seventeenth 26 and eighteenth 27 input field transistors, the nineteenth 28, the twentieth 29, the twenty-first 30, the twenty-second 31, the twenty-third 32 and the twenty-fourth 33 input field-effect transistors of a different type of conductivity, the first 34 current mirror, matched with the first 18 power supply bus, containing the first 35, the second 36, 37 third, 38 fourth and 39 fifth outputs, the input of which is connected to the first 1 input of the device, the second 40 and 41 third current mirrors, matched with the first 18 power supply bus, fourth 42, fifth 43, sixth 44, seventh 45, eighth 46 and ninth 47 current mirrors, matched with the second 19 power supply bus, tenth 48 current mirror lo, coordinated with the first 18 power supply bus and containing the first 49 and second 50 outputs, the input of which is connected to the second 2 input of the device, the first 51, the second 52, the third 53, the fourth 54, the fifth 55, the sixth 56, the seventh 57, the eighth 58 , ninth 59 and tenth 60 reference current sources, the first 35 output of the first 34 current mirror is connected to the combined sources of the first 4 and seventh 11 input field-effect transistors, the gate of the nineteenth 28 input field-effect transistor and is connected to the second 19 power supply bus through the first 51 reference current source , the drain of the nineteenth 28 input field-effect transistor is matched with the second 19 power supply bus, the sources of the nineteenth 28 and twentieth 29 input field-effect transistors are combined and connected to the first 18 power supply bus through the second 52 reference current source, the gate of the twentieth 29 input field-effect transistor is connected to the fifth 61 bias voltage source, the drain of the twentieth 29 input field-effect transistor is connected yon with the input of the fourth 42 current mirror, the second 36 output of the first 34 current mirror is connected to the combined sources of the second 5 and eighth 12 input field-effect transistors, the output of the fourth 42 current mirror and is connected to the first 18 power supply bus through the third 53 reference current source, the third 37 the output of the first 34 current mirror is connected to the combined sources of the third 6 and ninth 13 input field-effect transistors, the gate of the seventeenth 26 input field-effect transistor and is connected to the second 19 power supply bus through the fourth 54 reference current source, the fourth 38 output of the first 34 current mirror is connected to the input of the fifth 43 current mirror, the fifth 39 output of the first 34 current mirror is connected to the combined sources of the sixth 9 and twelfth 16 input field-effect transistors and connected to the output of the seventh 45 current mirror, the sources of the seventeenth 26 and eighteenth 27 input field-effect transistors are combined and connected to the second 19 power supply bus through five 55th reference current source, the drain of the seventeenth 26 input field-effect transistor is connected to the first 18 power supply bus, the drain of the eighteenth 27 input field-effect transistor is matched with the input of the second 40 current mirror, the gate of the eighteenth 27 input field-effect transistor is connected to the sixth 62 bias voltage source, the output of the fifth 43 of the current mirror is connected to the combined sources of the fourth 7 and tenth 14 input field-effect transistors and is matched with the first 18 power supply bus through the sixth 56 reference current source, the drain of the fourth 7 input field-effect transistor is connected to the input of the third 41 current mirror, the outputs of the second 40 and third 41 current mirrors are connected and connected to the combined sources of the fifth 8 and eleventh 15 input field-effect transistors, the drains of the eighth 12, eleventh 15 and twelfth 16 input field-effect transistors are combined and connected to the input of the sixth 44 current mirror, the output of which is matched with the output 3 of the device, per the output 49 of the tenth 48 current mirror is connected to the combined sources of the thirteenth 20 and fifteenth 23 input field-effect transistors, the gate of the twenty-first 30 input field-effect transistor and is connected to the second 19 power supply bus through the seventh 57 reference current source, the second 50 output of the eleventh 48 current mirror is connected with the combined sources of the fourteenth 21 and sixteenth 24 input field-effect transistors, the gate of the twenty-third 32 input field-effect transistor and is connected to the second 19 power supply bus through the ninth 59 reference current source, the sources of the twenty-first 30 and twenty-second 31 input field-effect transistors are combined and matched with the first 18 power supply bus through the eighth 58 reference current source, the drain of the twenty-second 31 input field-effect transistor is connected to the input of the seventh 45 current mirror, the gate of the twenty-second 31 input field-effect transistor is connected to the seventh 63 bias voltage source, the sources are twenty t the third 32 and twenty-fourth 33 input field-effect transistors are combined and connected to the first 18 power supply bus through the tenth 60 reference current source, the drain of the twenty-third 32 input field-effect transistor is connected to the input of the eighth 46 current mirror, the gate of the twenty-fourth 33 input field-effect transistor is connected to the eighth 64 bias voltage source, the drains of the twenty-first 30 and twenty-fourth 33 input field-effect transistors are combined and connected to the input of the ninth 47 current mirror, new connections are provided - the output of the third 41 current mirror is connected to the output of the ninth 47 current mirror, the output of the fourth 42 current mirror is connected to output of the eighth 46 current mirror.

In the drawing of FIG. 1 shows a diagram of a prototype, and the drawing of FIG. 2 is a diagram of the inventive current threshold element of the left cyclic shift on field-effect transistors in accordance with the claims.

In the drawing of FIG. 3 is a diagram of the current threshold element of the left cyclic shift of FIG. 2 in the Micro-Cap computer simulation environment on bipolar transistor models.

In the drawing of FIG. 4 shows waveforms of the input and output signals of the left cyclic shift circuit of FIG. 3.

Current threshold element left cyclic shift of FIG. 2 contains

first 1 and second 2 inputs of the device, output 3 of the device, first 4, second 5, third 6, fourth 7, fifth 8 and sixth 9 input field-effect transistors with combined gates, which are connected to the first 10 bias voltage source, seventh 11, eighth 12 , ninth 13, tenth 14, eleventh 15 and twelfth 16 input field-effect transistors of another type of conductivity with combined gates, which are connected to the second 17 bias voltage source, the drains of the first 4, second 5, third 6, fifth 8 and sixth 9 input field-effect transistors are connected with the first 18 power supply bus, the drains of the seventh 11, ninth 13 and tenth 14 input field-effect transistors are connected to the second 19 power supply bus, the thirteenth 20 and fourteenth 21 input field-effect transistors with combined gates, which are connected to the third 22 bias voltage source, the drains of the thirteenth 20th and 14th 21st input FETs are connected to the first 18th power supply rail, spots the twentieth 23 and sixteenth 24 input field-effect transistors of another type of conductivity with combined gates, which are connected to the fourth 25 bias voltage source, the drains of the fifteenth 23 and sixteenth 24 input field-effect transistors are connected to the second 19 power supply bus, the seventeenth 26 and eighteenth 27 input field-effect transistors, nineteenth 28, twentieth 29, twenty-first 30, twenty-second 31, twenty-third 32 and twenty-fourth 33 input field-effect transistors of a different type of conductivity, the first 34 current mirror matched with the first 18 power supply bus, containing the first 35, the second 36, the third 37 , the fourth 38 and 39 fifth outputs, the input of which is connected to the first 1 input of the device, the second 40 and 41 third current mirrors, matched with the first 18 power supply bus, the fourth 42, the fifth 43, the sixth 44, the seventh 45, the eighth 46 and the ninth 47 current mirrors, matched with the second 19 power supply bus, the tenth 48 current mirror, matched bathroom with the first 18 power supply bus and containing the first 49 and second 50 outputs, the input of which is connected to the second 2 input of the device, the first 51, the second 52, the third 53, the fourth 54, the fifth 55, the sixth 56, the seventh 57, the eighth 58, the ninth 59 and tenth 60 reference current sources, the first 35 output of the first 34 current mirror is connected to the combined sources of the first 4 and seventh 11 input field-effect transistors, the gate of the nineteenth 28 input field-effect transistor and is connected to the second 19 power supply bus through the first 51 reference current source, drain nineteenth 28 input field-effect transistor matched with the second 19 power supply bus, the sources of the nineteenth 28 and twentieth 29 input field-effect transistors are combined and connected to the first 18 power supply bus through the second 52 reference current source, the gate of the twentieth 29 input field-effect transistor is connected to the fifth 61 voltage source bias, the drain of the twentieth 29th input field-effect transistor is connected to the input m of the fourth 42 current mirror, the second 36 output of the first 34 current mirror is connected to the combined sources of the second 5 and eighth 12 input field-effect transistors, the output of the fourth 42 current mirror and is connected to the first 18 power supply bus through the third 53 reference current source, the third 37 output of the first 34 current mirror is connected to the combined sources of the third 6 and ninth 13 input field-effect transistors, the gate of the seventeenth 26 input field-effect transistor and is connected to the second 19 power supply bus through the fourth 54 reference current source, the fourth 38 output of the first 34 current mirror is connected to the input of the fifth 43 current mirrors, the fifth 39 output of the first 34 current mirror is connected to the combined sources of the sixth 9 and twelfth 16 input field-effect transistors and is connected to the output of the seventh 45 current mirror, the sources of the seventeenth 26 and eighteenth 27 input field-effect transistors are combined and connected to the second 19 power supply bus through the fifth 55 isto reference current source, the drain of the seventeenth 26 input field-effect transistor is connected to the first 18 power supply bus, the drain of the eighteenth 27 input field-effect transistor is matched with the input of the second 40 current mirror, the gate of the eighteenth 27 input field-effect transistor is connected to the sixth 62 source of bias voltage, the output of the fifth 43 current the mirror is connected to the combined sources of the fourth 7 and tenth 14 input field-effect transistors and is matched with the first 18 power supply bus through the sixth 56 reference current source, the drain of the fourth 7 input field-effect transistor is connected to the input of the third 41 current mirror, the outputs of the second 40 and third 41 current mirrors connected and connected to the combined sources of the fifth 8 and eleventh 15 input field-effect transistors, the drains of the eighth 12, eleventh 15 and twelfth 16 input field-effect transistors are combined and connected to the input of the sixth 44 current mirror, the output of which is matched with the output 3 of the device, the first 49 output d tenth 48 current mirror is connected to the combined sources of the thirteenth 20 and fifteenth 23 input field-effect transistors, the gate of the twenty-first 30 input field-effect transistor and is connected to the second 19 power supply bus through the seventh 57 reference current source, the second 50 output of the eleventh 48 current mirror is connected to the combined the sources of the fourteenth 21 and sixteenth 24 input field-effect transistors, the gate of the twenty-third 32 input field-effect transistor and is connected to the second 19 power supply bus through the ninth 59 reference current source, the sources of the twenty-first 30 and twenty-second 31 input field-effect transistors are combined and matched with the first 18 bus power sources through the eighth 58 reference current source, the drain of the twenty-second 31 input field-effect transistor is connected to the input of the seventh 45 current mirror, the gate of the twenty-second 31 input field-effect transistor is connected to the seventh 63 bias voltage source, the sources of the twenty-third 32 and twenty-fourth 33 input field-effect transistors are combined and connected to the first 18 power supply bus through the tenth 60 reference current source, the drain of the twenty-third 32 input field-effect transistor is connected to the input of the eighth 46 current mirror, the gate of the twenty-fourth 33 input field-effect transistor is connected to the eighth 64 source bias voltage drains twenty-first 30 and twenty-fourth 33 input field-effect transistors are combined and connected to the input of the ninth 47 current mirror. New connections have been introduced into the circuit - the output of the third 41 current mirror is connected to the output of the ninth 47 current mirror, the output of the fourth 42 current mirror is connected to the output of the eighth 46 current mirror.

Consider the operation of the proposed logic element circuit of Fig.2.

имеет вид:Function truth table

looks like:

для троичных переменных, функцию y запишем в следующем виде:Given that

for ternary variables, we write the function y in the following form:

при i=1 и переменная

при i=2.Expression (1) is implemented by the circuit of Fig. 2, the output is the variable x at i=0. Variable

for i=1 and the variable

for i=2.

. Входная переменная «i» в виде сигнала втекающего тока поступает на второй 2 вход устройства и далее на вход десятого 48 токового зеркала. Выходной сигнал с первого 49 выхода десятого 48 токового зеркала подаётся на объединённые истоки тринадцатого 20 и пятнадцатого 23 входных полевых транзисторов, а затем на затвор двадцать первого 30 входного полевого транзистора. Режимы работы тринадцатого 20 и пятнадцатого 23 входных полевых транзисторов задаются значениями напряжений третьего 22 и четвертого 25 источников напряжения смещения. Двадцать первый 30 и двадцать второй 31 входные полевые транзисторы образуют ДК, переключение токов стоков этих транзисторов определяется сигналом, поступающим на затвор двадцать первого 30 входного полевого транзистора. ДК в данном случае выполняет функции порогового элемента, выполняя сравнение переменной (i > 0,5) c пороговым уровнем седьмого 57 источника опорного тока. Выбор такого порогового уровня обеспечивает независимость результатов преобразования сигналов от погрешностей преобразования в пределах диапазона изменения тока 0,5I₀. При положительной разности сигналов (i - 0,5) ток восьмого 58 источника опорного тока через сток двадцать второго 31 входного полевого транзистора подается на вход седьмого 45 токового зеркала. На выходе седьмого 45 токового зеркала формируется сигнал «запрет», разрешая передачу сигнала с пятого 39 выхода первого 34 токового зеркала только при i=0, таким образом, формируя первое слагаемое выражения (1). Выходной сигнал со второго 50 выхода десятого 48 токового зеркала подаётся на объединённые истоки четырнадцатого 21 и шестнадцатого 24 входных полевых транзисторов, а затем на затвор двадцать третьего 32 входного полевого транзистора. Режимы работы четырнадцатого 21 и шестнадцатого 24 входных полевых транзисторов задаются значениями напряжений третьего 22 и четвертого 25 источников напряжения смещения. Двадцать третий 32 и двадцать четвёртый 33 входные полевые транзисторы образуют ДК, переключение токов стоков этих транзисторов определяется сигналом, поступающим на затвор двадцать третьего 32 входного полевого транзистора. ДК в данном случае выполняет функции порогового элемента, выполняя сравнение переменной (i < 0,5) c пороговым уровнем девятого 59 источника опорного тока. Выбор такого порогового уровня обеспечивает независимость результатов преобразования сигналов от погрешностей преобразования в пределах диапазона изменения тока 0,5I₀. При положительной разности сигналов (i - 0,5) ток десятого 60 источника опорного тока через сток двадцать четвёртого 33 входного полевого транзистора подается на вход девятого 47 токового зеркала. На выходе девятого 47 токового зеркала формируется сигнал «запрет», разрешая передачу сигнала с выхода третьего 41 токового зеркала только при i=2, таким образом, формируя третье слагаемое выражения (1). Выходной сигнал со стока двадцать первого 30 входного полевого транзистора складывается с выходным сигналом со стока двадцать четвертого 33 входного полевого транзистора и подается на вход девятого 47 токового зеркала. На выходе девятого 47 токового зеркала формируется сигнал «запрет», разрешая передачу сигнала

только при i=1, таким образом, формируя второе слагаемое выражения (1). Выходной сигнал со второго 36 выхода первого 34 токового зеркала складывается с сигналом третьего 53 источника опорного тока и подаётся на объединённые истоки второго 5 и восьмого 12 входных полевых транзисторов, где из данного сигнала вычитаются токи с выходов четвертого 42 и девятого 47 токовых зеркал. При положительном значении алгебраической суммы этих токов через сток восьмого 12 входного полевого транзистора ток, определяемый вторым слагаемым выражения (1) поступает на вход шестого 44 токового зеркала и далее на выход логического элемента.The input variable "x ₁ " in the form of an incoming current signal is fed to the first 1 input of the device and then to the input of the first 34 current mirror. The output signal from the first 35 output of the first 34 current mirror is fed to the combined sources of the first 4 and seventh 11 input field-effect transistors, and then to the gate of the nineteenth 28 input field-effect transistor, where the current of the first 51 reference current source is subtracted from this signal. Modes of operation of the first 4 and seventh 11 input field-effect transistors are set by the voltage values of the first 10 and second 17 bias voltage sources. Nineteenth 28 and 29th 29th input field-effect transistors form a DC, switching the drain currents of these transistors is determined by the signal arriving at the gate of the nineteenth 28th input field-effect transistor. DC in this case performs the functions of a threshold element, comparing the variable (i < 1.5) with the threshold level set by the first 51 reference current sources. The choice of such a threshold level ensures the independence of the results of signal conversion from conversion errors within the range of current change 0.5I ₀ . With a positive signal difference (i - 1) the current of the second 52 reference current source through the drain of the twentieth 29 input field-effect transistor is fed to the input of the fourth 42 current mirror. The output signal from the second 36 output of the first 34 current mirror is added to the signal of the third 53 reference current source, and the output current from the output of the fourth 42 current mirror is subtracted from the resulting sum, forming a signal

. The input variable "i" in the form of an incoming current signal is fed to the second 2 input of the device and then to the input of the tenth 48 current mirror. The output signal from the first 49 output of the tenth 48 current mirror is fed to the combined sources of the thirteenth 20 and fifteenth 23 input field-effect transistors, and then to the gate of the twenty-first 30 input field-effect transistor. Modes of operation of the thirteenth 20 and fifteenth 23 input field-effect transistors are set by the voltage values of the third 22 and fourth 25 bias voltage sources. The twenty-first 30 and twenty-second 31 input field-effect transistors form a DC, the switching of the currents of the drains of these transistors is determined by the signal arriving at the gate of the twenty-first 30 input field-effect transistor. DC in this case performs the functions of a threshold element, comparing the variable (i > 0.5) with the threshold level of the seventh 57 reference current source. The choice of such a threshold level ensures the independence of the results of signal conversion from conversion errors within the range of current change 0.5I ₀ . With a positive signal difference (i - 0.5) the current of the eighth 58 reference current source through the drain of the twenty-second 31 input field-effect transistor is fed to the input of the seventh 45 current mirror. At the output of the seventh 45 current mirror, a "prohibition" signal is generated, allowing the signal to be transmitted from the fifth 39 output of the first 34 current mirror only when i=0, thus forming the first term of the expression (1). The output signal from the second 50 output of the tenth 48 current mirror is fed to the combined sources of the fourteenth 21 and sixteenth 24 input field-effect transistors, and then to the gate of the twenty-third 32 input field-effect transistor. Modes of operation of the fourteenth 21 and sixteenth 24 input field-effect transistors are set by the voltage values of the third 22 and fourth 25 bias voltage sources. Twenty-third 32 and twenty-fourth 33 input field-effect transistors form a DC, switching the drain currents of these transistors is determined by the signal arriving at the gate of the twenty-third 32 input field-effect transistor. DC in this case performs the functions of a threshold element, comparing the variable (i < 0.5) with the threshold level of the ninth 59 reference current source. The choice of such a threshold level ensures the independence of the results of signal conversion from conversion errors within the range of current change 0.5I ₀ . With a positive signal difference (i - 0.5), the current of the tenth 60 reference current source through the drain of the twenty-fourth 33 input field-effect transistor is fed to the input of the ninth 47 current mirror. At the output of the ninth 47 current mirror, a "prohibition" signal is generated, allowing the signal to be transmitted from the output of the third 41 current mirror only when i=2, thus forming the third term of the expression (1). The output signal from the drain of the twenty-first 30 input FET is added to the output signal from the drain of the twenty-fourth 33 input FET and is fed to the input of the ninth 47 current mirror. At the output of the ninth 47 current mirror, a "prohibition" signal is generated, allowing signal transmission

only when i=1, thus forming the second term of the expression (1). The output signal from the second 36 output of the first 34 current mirror is added to the signal of the third 53 reference current source and is fed to the combined sources of the second 5 and eighth 12 input field-effect transistors, where currents from the outputs of the fourth 42 and ninth 47 current mirrors are subtracted from this signal. With a positive value of the algebraic sum of these currents through the drain of the eighth 12 input field-effect transistor, the current determined by the second term of expression (1) is fed to the input of the sixth 44 current mirror and then to the output of the logic element.

, и совместно с сигналом «запрет» на выходе девятого 47 токового зеркала через сток одиннадцатого 15 входного полевого транзистора поступает на вход шестого 44 токового зеркала и далее на выход логического элемента. Режимы работы одиннадцатого 15 входного полевого транзистора задаётся значениями напряжения второго 17 источника напряжения смещения. Выходной сигнал с четвертого 38 выхода первого 34 токового зеркала подаётся на вход пятого 43 токового зеркала. Из сигнала с выхода пятого 43 токового зеркала вычитается ток шестого 56 источника тока и подаётся на объединённые истоки четвертого 7 и десятого 14 входных полевых транзисторов. Режимы работы четвертого 7 и десятого 14 входных полевых транзисторов задаются значениями напряжений первого 10 и второго 17 источников напряжения смещения. Сигнал со стока четвертого 7 входного полевого транзистора подаётся на вход третьего 41 токового зеркала. Выходной сигнал с пятого 39 выхода первого 34 токового зеркала вычитается из сигнала с выхода седьмого 45 токового зеркала и подаётся на объединённые истоки шестого 9 и двенадцатого 16 входных полевых транзисторов. Режимы работы шестого 9 и двенадцатого 16 входных полевых транзисторов задаются значениями напряжений первого 10 и второго 17 источников напряжения смещения. Сигнал со стока двенадцатого 16 входного полевого транзистора складывается с сигналами со стоков восьмого 12 и одиннадцатого 15 входных полевых транзисторов, и подаются на вход шестого 44 токового зеркала, где преобразуются в равный им вытекающий ток и передаются на выход 3 устройства.Modes of operation of the second 5 and eighth 12 input field-effect transistors are set by the voltage values of the first 10 and second 17 bias voltage sources. The output signal from the third 37 output of the first 34 current mirror is fed to the combined sources of the third 6 and ninth 13 input field-effect transistors, and then to the gate of the seventeenth 26 input field-effect transistor, where the current of the fourth 54 reference current source is subtracted from this signal. Modes of operation of the second 5 and eighth 12 input field-effect transistors are set by the voltage values of the first 10 and second 17 bias voltage sources. The seventeenth 26 and eighteenth 27 input field-effect transistors form a DC, the switching of the drain currents of these transistors is determined by the signal arriving at the gate of the seventeenth 26 input field-effect transistor. DC in this case performs the functions of a threshold element, performing a comparison of the variable (i > 0.5) with the threshold level of the fourth 54 reference current source. The choice of such a threshold level ensures the independence of the results of signal conversion from conversion errors within the range of current change 0.5I ₀ . With a positive signal difference (i - 0.5) the current of the fifth 55 reference current source through the drain of the eighteenth 27 input field-effect transistor is fed to the input of the second 40 current mirror. The signal from the output of the second 40 current mirror is added to the output current of the third 41 current mirror, forming a signal

, and together with the signal "prohibition" at the output of the ninth 47 current mirror through the drain of the eleventh 15 input field-effect transistor is fed to the input of the sixth 44 current mirror and then to the output of the logic element. Operating modes of the eleventh 15 input field-effect transistor is set by the voltage values of the second 17 bias voltage source. The output signal from the fourth 38 output of the first 34 current mirror is fed to the input of the fifth 43 current mirror. The current of the sixth 56 current source is subtracted from the output signal of the fifth 43 current mirror and fed to the combined sources of the fourth 7 and tenth 14 input field-effect transistors. Modes of operation of the fourth 7 and tenth 14 input field-effect transistors are set by the voltage values of the first 10 and second 17 bias voltage sources. The signal from the drain of the fourth 7 input field-effect transistor is fed to the input of the third 41 current mirror. The output signal from the fifth 39 output of the first 34 current mirror is subtracted from the signal from the output of the seventh 45 current mirror and is fed to the combined sources of the sixth 9 and twelfth 16 input field-effect transistors. Modes of operation of the sixth 9 and twelfth 16 input field-effect transistors are set by the voltage values of the first 10 and second 17 bias voltage sources. The signal from the drain of the twelfth 16 input field-effect transistor is added to the signals from the drains of the eighth 12 and eleventh 15 input field-effect transistors, and is fed to the input of the sixth 44 current mirror, where it is converted into an equal flowing current and transmitted to the output 3 of the device.

In the diagram in Fig. 2 two-terminal 65 is used to detect the presence of a current quantum in the output circuit in the process of experimental research.

Shown in FIG. 4, the simulation results confirm the indicated properties of the proposed scheme.

Thus, the considered circuit solution of the current threshold element of the left cyclic shift is characterized by a multi-valued state of internal signals and signals at its current inputs and outputs, which can be used as the basis for computing and control devices using multi-valued linear algebra, a special case of which is Boolean algebra.

REFERENCES

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2. Patent US 6.700.413, 2004

3. Patent US 6.414.519, 2002

4. Patent US 6.566.912, 2003

5. Patent application US 2007/0018694, 2007

6. Patent application US 2004/0263210, 2004

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Claims (1)

Current threshold element of the left cyclic shift, containing the first (1) and second (2) inputs of the device, the output (3) of the device, the first (4), the second (5), the third (6), the fourth (7), the fifth (8) and sixth (9) input FETs with combined gates, which are connected to the first (10) bias voltage source, seventh (11), eighth (12), ninth (13), tenth (14), eleventh (15) and twelfth ( 16) input field-effect transistors of a different type of conductivity with combined gates, which are connected to the second (17) bias voltage source, drains of the first (4), second (5), third (6), fifth (8) and sixth (9) input field transistors are connected to the first (18) power supply bus, the drains of the seventh (11), ninth (13) and tenth (14) input field-effect transistors are connected to the second (19) power supply bus, the thirteenth (20) and fourteenth (21) input field-effect transistors transistors with combined gates, which are connected to the third (22) bias voltage source, the drains of the thirteenth (20) and fourteenth (21) input field-effect transistors are connected to the first (18) power supply bus, the fifteenth (23) and sixteenth (24) input field-effect transistors of a different type of conductivity with combined gates, which are connected to the fourth (25) source bias voltages, the drains of the fifteenth (23) and sixteenth (24) input FETs are connected to the second (19) power supply bus, the seventeenth (26) and eighteenth (27) input FETs, the nineteenth (28), twentieth (29), twenty the first (30), twenty-second (31), twenty-third (32) and twenty-fourth (33) input field-effect transistors of a different conductivity type, the first (34) current mirror matched with the first (18) power supply bus, containing the first (35 ), second (36), third (37), fourth (38) and fifth (39) outputs, the input of which is connected to the first (1) input of the device, the second (40) and third (41) current mirrors matched with the first ( 18) power supply bus current mirrors, fourth (42), fifth (43), sixth (44), seventh (45), eighth (46), and ninth (47) current mirrors matched with the second (19) power supply bus, tenth (48) current mirror , matched with the first (18) power supply bus and containing the first (49) and second (50) outputs, the input of which is connected to the second (2) input of the device, the first (51), second (52), third (53), fourth (54), fifth (55), sixth (56), seventh (57), eighth (58), ninth (59) and tenth (60) reference current sources, the first (35) output of the first (34) current mirror is connected to the combined sources of the first (4) and seventh (11) input field-effect transistors, the gate of the nineteenth (28) input field-effect transistor and is connected to the second (19) power supply bus through the first (51) reference current source, the drain of the nineteenth (28) input field-effect transistor matched with the second (19) power supply bus, the sources of the nineteenth (28) and twentieth (29) input field-effect transistors are combined and connected with the first (18) power supply bus through the second (52) reference current source, the gate of the twentieth (29) input FET is connected to the fifth (61) bias voltage source, the drain of the twentieth (29) input FET is connected to the input of the fourth (42) current mirror, the second (36) output of the first (34) current mirror is connected to the combined sources of the second (5) and eighth (12) input field-effect transistors, the output of the fourth (42) current mirror and is connected to the first (18) power supply bus through the third (53) reference current source, the third (37) output of the first (34) current mirror is connected to the combined sources of the third (6) and ninth (13) input field-effect transistors, the gate of the seventeenth (26) input field-effect transistor and is connected to the second (19) power supply bus through the fourth (54) reference current source, the fourth (38) output of the first (34) current mirror is connected to the input of the fifth (43) current mirror, the fifth (39) output of the first (34) current mirror ala is connected to the combined sources of the sixth (9) and twelfth (16) input field-effect transistors and connected to the output of the seventh (45) current mirror, the sources of the seventeenth (26) and eighteenth (27) input field-effect transistors are combined and connected to the second (19) bus power sources through the fifth (55) reference current source, the drain of the seventeenth (26) input field-effect transistor is connected to the first (18) power supply bus, the drain of the eighteenth (27) input field-effect transistor is matched with the input of the second (40) current mirror, the gate of the eighteenth ( 27) the input field-effect transistor is connected to the sixth (62) bias voltage source, the output of the fifth (43) current mirror is connected to the combined sources of the fourth (7) and tenth (14) input field-effect transistors and is matched with the first (18) power supply bus through the sixth (56) reference current source, the drain of the fourth (7) input field-effect transistor is connected to the input of the third (41) current mirror, the outputs of the second (40) and t of the third (41) current mirrors are connected and connected to the combined sources of the fifth (8) and eleventh (15) input field-effect transistors, the drains of the eighth (12), eleventh (15) and twelfth (16) input field-effect transistors are combined and connected to the input of the sixth ( 44) current mirror, the output of which is matched with the output (3) of the device, the first (49) output of the tenth (48) current mirror is connected to the combined sources of the thirteenth (20) and fifteenth (23) input field-effect transistors, the gate of the twenty-first (30) input field-effect transistor and is connected to the second (19) power supply bus through the seventh (57) reference current source, the second (50) output of the eleventh (48) current mirror is connected to the combined sources of the fourteenth (21) and sixteenth (24) input field-effect transistors, the gate twenty-third (32) input field-effect transistor and is connected to the second (19) power supply bus through the ninth (59) reference current source, sources of the twenty-first (30) and twenty watts Three (31) input field-effect transistors are combined and matched with the first (18) power supply bus through the eighth (58) reference current source, the drain of the twenty-second (31) input field-effect transistor is connected to the input of the seventh (45) current mirror, the gate of the twenty-second ( 31) the input FET is connected to the seventh (63) bias voltage source, the sources of the twenty-third (32) and twenty-fourth (33) input FETs are combined and connected to the first (18) power supply bus through the tenth (60) reference current source, the drain of the twenty-third (32) input field-effect transistor is connected to the input of the eighth (46) current mirror, the gate of the twenty-fourth (33) input field-effect transistor is connected to the eighth (64) bias voltage source, the drains of the twenty-first (30) and twenty-fourth (33) input field effect transistors are combined and connected to the input of the ninth (47) current mirror, characterized in that the output of the third (41) current mirror is connected to the output of the ninth (47) current mirror, the output of the fourth (42) current mirror is connected to the output of the eighth (46) current mirror.

Images