RU2725149C1 - Right cyclic shift current threshold element - Google Patents

Abstract

FIELD: radio engineering; analogue microelectronics.SUBSTANCE: invention relates to radio engineering and analogue microelectronics and can be used in high-speed analogue and analogue-to-digital interfaces for processing signals of sensors.EFFECT: technical result consists in creation of current threshold element of right cyclic shift, in which internal conversion of information is carried out in current form of signals, which increases speed of information conversion devices.1 cl, 1 tbl, 4 dwg

Description

The alleged invention relates to the field of computer engineering, automation, communication and can be used in various digital structures and systems of automatic control, transmission of digital information, etc.

Comparators implemented on the basis of emitter-coupled logic [1-14], operating according to the laws of Boolean algebra and having two logical states “0” and “1”, characterized by low and high potentials, are widely used in various computing and control systems. Currently, the binary element base has almost reached the limit of functional capabilities, one of the promising ways to further increase the efficiency of digital devices is the transition from binary Boolean functions to multi-valued logical functions and the implementation of the corresponding multi-valued elemental base.

In the patent [15], articles [16-19], as well as monographs [20-21] it is shown that Boolean algebra is a special case of more general linear algebra, the practical implementation of which in the structure of computing and logical devices of automation of a new generation requires the creation of a special elemental base, implemented on the basis of logic with a multi-valued internal representation of signals, in which the current quantum I ₀ is the equivalent of a standard logical signal. The inventive device "Current threshold element of the right cyclic shift" refers to this type of logic elements. The cyclic shift logical function for k-valued variables is a natural generalization of the inversion logical function, defined only for Boolean binary variables, i.e. the logical element of the right cyclic shift is a generalization of the element NOT for variables with significance greater than 2.

The closest prototype of the claimed device is a logic element presented in patent RU 2692573 "Current threshold logic element" Disambiguity ", IPC H03K 19/21, H03K 19/00, 2019). It contains (Fig. 1) the first 1 and second 2 inputs of the device, output 3 of the device, the first 4, second 5 and third 6 input field-effect transistors with integrated gates that are connected to the first 7 bias voltage source, the fourth 8, fifth 9 and sixth 10 input field effect transistors of a different type of conductivity with integrated gates that are connected to the second 11 source of bias voltage, the sources of the first 4 and fourth 8 input field effect transistors are connected to each other, the sources of the second 5 and fifth 9 input field effect transistors are connected to each other, the sources of the third 6 and the sixth 10 input field-effect transistors are connected to each other, the first 12 current mirror, matched with the first 13 bus power supply, the input of which is connected to the drain of the sixth 10 input field-effect transistor, the output of which is connected to the output 3 of the device, the second 14 current mirror, matched with the first 13 bus power supply, the output of which is connected to the combined sources of the third 6 and there are 10 input field-effect transistors, a third 15 current mirror, matched to the first 13 bus of the power source, a fourth 16 current mirror, matched to the second 17 bus of the power source, containing the first 18 and second 19 outputs, the input of which is connected to the input 2 of the device, the fifth 20 a current mirror, matched to the second 17 bus of the power source, the output of the third 15 current mirror is connected to the second 17 bus of the power source through the first 21 sources of reference current, the first 18 output of the fourth 16 current mirror is connected to the first 13 bus of the power source through the second 22 source of reference current and connected to the combined sources of the first 4 and fourth 8 input field-effect transistors, the seventh 23 and eighth 24 input field-effect transistors, the sources of which are combined and connected to the second 17 bus power supply through the third 25 source of reference current, the gate of the seventh 23 input field-effect transistor is connected to the combined the sources of the first 4 and fourth 8 input transistor ditch, the drain of the eighth 24 input field-effect transistor is connected to the input of the second 14 current mirror, the ninth 26 and tenth 27 input field-effect transistors of a different type of conductivity, the sources of which are combined and connected to the first 13 bus of the power supply through the fourth 28 reference current source, the drain of the tenth 27 input the field-effect transistor is connected to the input of the fifth 20 current mirror, the gate of the ninth 26 input field-effect transistor is connected to the combined sources of the second 5 and fifth 9 input field-effect transistors, the drains of the first 4, second 5, third 6 and ninth 26 input field-effect transistors are connected to the second 17 source bus power supply, drains of the fourth 8 and fifth 9 input field-effect transistors are connected to the first 13 bus of the power source, the third 29 bias voltage source is connected to the gate of the eighth 24 input field-effect transistor, the fourth 30 bias voltage source is connected to the gate of the tenth 27 input field-effect transistor.

A significant drawback of the known logical element is that it implements a binary Boolean function and does not provide the ability to work with multi-valued input and output current signals, which ultimately leads to a reduction in functionality and a decrease in its speed. This does not allow creating a functionally complete basis of digital technology, an indispensable element of which is the implementation of the cyclic shift operation, the generalized equivalent of the inversion operation. This does not allow to create a complete basis of computer technology, operating on the principles of converting multivalued current signals. The use of threshold functions and their corresponding threshold elements, in addition to the implementation of a given logical function, provides scaling and normalization of the levels of output signals and thereby eliminates all signal errors that occur before the threshold element.

The main objective of the invention is to create a current threshold element of the right cyclic shift, in which the internal transformation of information is carried out in the current form of signals. Ultimately, this allows you to improve performance and create an elemental base of digital devices operating on the principles of multi-valued linear algebra [20-21].

The problem is solved in that in a logical element (figure 1),

containing the first 1 and second 2 inputs of the device, the output of 3 devices, the first 4, second 5 and third 6 input field-effect transistors with combined gates that are connected to the first 7 bias voltage source, the fourth 8, fifth 9 and sixth 10 other type of field effect transistors conductivity with combined gates that are connected to the second 11 source of bias voltage, the sources of the first 4 and fourth 8 input field effect transistors are connected to each other, the sources of the second 5 and fifth 9 input field effect transistors are connected to each other, the sources of the third 6 and sixth 10 input field effect transistors transistors are connected to each other, the first 12 current mirror, matched with the first 13 bus power source, the input of which is connected to the drain of the sixth 10 input field-effect transistor, the output of which is connected to the output 3 of the device, the second 14 current mirror, matched with the first 13 bus power source whose output is connected to the combined sources of the third 6 and sixth 10 input one field-effect transistor, a third 15 current mirror, matched with the first 13 bus of the power source, a fourth 16 current mirror, matched with the second 17 bus of the power source, containing the first 18 and second 19 outputs, the input of which is connected to the input 2 of the device, the fifth 20 current mirror coordinated with the second 17 bus of the power source, the output of the third 15 current mirror is connected to the second 17 bus of the power source through the first 21 current source, the first 18 output of the fourth 16 current mirror is connected to the first 13 bus of the power source through the second 22 current source and connected with the combined sources of the first 4 and fourth 8 input field-effect transistors, the seventh 23 and eighth 24 input field-effect transistors, the sources of which are combined and connected to the second 17 bus of the power source through the third 25 source of reference current, the gate of the seventh 23 input field-effect transistor is connected to the combined sources of the first 4 and fourth 8 input field effect transistors, drain the eighth 24 input field-effect transistor is connected to the input of the second 14 current mirror, the ninth 26 and tenth 27 input field-effect transistors of another type of conductivity, the sources of which are combined and connected to the first 13 bus of the power source through the fourth 28 source of reference current, the drain of the tenth 27 input field-effect transistor is connected to the input of the fifth 20 current mirror, the gate of the ninth 26 input field-effect transistor is connected to the combined sources of the second 5 and fifth 9 input field-effect transistors, the drains of the first 4, second 5, third 6 and ninth 26 input field-effect transistors are connected to the second 17 bus of the power supply, drains the fourth 8 and fifth 9 input field-effect transistors are connected to the first 13 bus of the power supply, the third 29 bias voltage source is connected to the gate of the eighth 24 input field-effect transistor, the fourth 30 bias voltage source is connected to the gate of the tenth 27 input field-effect transistor, new elements and communications are provided - in circuits u introduced the first 31 additional current mirror, consistent with the second 17 bus power source, containing the first 32, second 33, third 34, fourth 35 and fifth 36 outputs, the input of which is connected to input 1 of the device, the second 37 additional current mirror, matched with the second 17 power supply bus, third 38, fourth 39 and fifth 40 additional current mirrors, consistent with the first 13 power supply bus, first 41, second 42, third 43, fourth 44 and fifth 45 additional input field effect transistors with integrated gates that are connected to the first 7 source of bias voltage, the sixth 46, seventh 47, eighth 48, ninth 49 and tenth 50 additional input field effect transistors with integrated gates that are connected to the second 11 source of bias voltage, the first 51 additional source of reference current, the eleventh 52 and twelfth 53 additional input field-effect transistors whose sources are connected and connected to the second 17 bus power supply through the second 54 additional reference current source, third 55, fourth 56 and fifth 57 additional reference current sources, thirteenth 58 and fourteenth 59 additional input field effect transistors, the sources of which are connected and connected to the second 17 bus power source through the sixth 60 additional reference source current, the sources of the first 41 and sixth 46 additional input field effect transistors are connected to each other, the sources of the second 42 and seventh 47 additional input field effect transistors are connected to each other, the sources of the third 43 and eighth 48 additional input field effect transistors are connected to each other, the sources of the fourth 44 and the ninth 49 additional input field effect transistors are connected to each other, the sources of the fifth 45 and tenth 50 additional input field effect transistors are connected to each other, the drains of the first 41, second 42, fourth 44 and fifth 45 additional input field effect transistors are connected to the second 17 source bus power supply, drains of the sixth 46, eighth 48, tenth 50 and eleventh 52 additional input field-effect transistors are connected to the first 13 bus of the power supply, the first 32 output of the first 31 additional current mirrors is connected to the first 13 bus of the power supply through the first 51 additional reference current source and connected to the combined sources of the first 41 and sixth 46 additional input field-effect transistors and the gate of the eleventh 52 additional input field-effect transistor, the second 33 output of the first 31 additional current mirrors is connected to the second 17 bus power source through the third 55 additional reference current source and connected to the combined sources of the second 42 and seventh 47 additional input field-effect transistors and outputs of the third 38 and fifth 40 additional current mirrors, the third 34 output of the first 31 additional current mirrors is connected to the first 13 bus power source through the fourth 56 additional reference current source and connected to the combined sources of the second 5 and fourth 9 input field-effect transistors, the fourth 35 output of the first 31 additional current mirrors connected to the input of the third 15 current mirrors, the fifth 36 output of the first 31 additional current mirrors connected to the combined sources of the third 6 and sixth 10 input field-effect transistors, stock twelfth 53 additional input field effect transistor is connected to the input of the third 38 additional current mirror, drains of the seventh 47 and ninth 49 additional input field effect transistors are connected to each other and connected to the input of the first 12 current mirror, the drain of the third 43 additional input field effect transistor is connected to the input of the second 37 additional the current mirror, the outputs of the fifth 20 current mirror and the second 37 additional current mirrors are connected and connected to the combined sources of the fourth 44 and ninth 49 additional input field-effect transistors and the output of the fourth 39 additional current mirror, the output of the third 15 current mirror is connected to the combined sources of the third 43 and eighth 48 additional input field-effect transistors, the input of the fourth 39 additional current mirror is connected to the drain of the thirteenth 58 additional input field-effect transistor, the drains of the seventh 23 input field-effect transistor and the fourteenth 59 additional input field-effect transistor are connected to each other with another and connected to the input of the fifth 40 additional current mirror, the second 19 output of the fourth 16 current mirror is connected to the first 13 bus of the power source through the fifth 57 additional reference current source and is connected to the combined sources of the fifth 45 and tenth 50 additional input field-effect transistors and to the gate thirteenth 58 additional input field effect transistor, the gate of the twelfth 53 additional input field effect transistor is connected to the fourth 30 source of bias voltage, the gate of the fourteenth 59 additional input field effect transistor is connected It is juxtaposed to the third 29th bias voltage source.

In the drawing of FIG. 1 shows a diagram of a prototype, and in the drawing of FIG. 2 is a diagram of the claimed current threshold element of the right cyclic shift on field-effect transistors in accordance with claim 1.

In the drawing of FIG. 3 is a diagram of the inventive device of FIG. 2 in the computer simulation environment Micro-Cap models of field-effect transistors.

In the drawing of FIG. 4 shows the waveforms of the input and output signals of the right cyclic shift circuit of FIG. 3.

Current threshold element right cyclic shift of FIG. 2 contains the first 1 and second 2 inputs of the device, the output of 3 devices, the first 4, second 5 and third 6 input field effect transistors with combined gates that are connected to the first 7 bias voltage source, the fourth 8, fifth 9 and sixth 10 input field effect transistors of another conductivity type with combined gates that are connected to the second 11 bias voltage source, the sources of the first 4 and fourth 8 input field-effect transistors are connected to each other, the sources of the second 5 and fifth 9 input field-effect transistors are connected to each other, the sources of the third 6 and sixth 10 input field-effect transistors are connected to each other, the first 12 current mirror, matched with the first 13 bus power supply, the input of which is connected to the drain of the sixth 10 input field-effect transistor, the output of which is connected to the output 3 of the device, the second 14 current mirror, matched with the first 13 bus source power supply, the output of which is connected to the combined sources of the third 6 and sixth 10 input one field-effect transistor, a third 15 current mirror, matched with the first 13 bus of the power source, a fourth 16 current mirror, matched with the second 17 bus of the power source, containing the first 18 and second 19 outputs, the input of which is connected to the input 2 of the device, the fifth 20 current mirror coordinated with the second 17 bus of the power source, the output of the third 15 current mirror is connected to the second 17 bus of the power source through the first 21 current source, the first 18 output of the fourth 16 current mirror is connected to the first 13 bus of the power source through the second 22 current source and connected with the combined sources of the first 4 and fourth 8 input field-effect transistors, the seventh 23 and eighth 24 input field-effect transistors, the sources of which are combined and connected to the second 17 bus of the power source through the third 25 source of reference current, the gate of the seventh 23 input field-effect transistor is connected to the combined sources of the first 4 and fourth 8 input field effect transistors, drain the eighth 24 input field-effect transistor is connected to the input of the second 14 current mirror, the ninth 26 and tenth 27 input field-effect transistors of another type of conductivity, the sources of which are combined and connected to the first 13 bus of the power source through the fourth 28 source of reference current, the drain of the tenth 27 input field-effect transistor is connected to the input of the fifth 20 current mirror, the gate of the ninth 26 input field-effect transistor is connected to the combined sources of the second 5 and fifth 9 input field-effect transistors, the drains of the first 4, second 5, third 6 and ninth 26 input field-effect transistors are connected to the second 17 bus of the power supply, drains the fourth 8 and fifth 9 input field-effect transistors are connected to the first 13 bus of the power source, the third 29 bias voltage source is connected to the gate of the eighth 24 input field-effect transistor, the fourth 30 bias voltage source is connected to the gate of the tenth 27 input field-effect transistor. The first 31 additional current mirrors are introduced into the circuit, coordinated with the second 17 power supply bus, containing the first 32, second 33, third 34, fourth 35 and fifth 36 outputs, the input of which is connected to the input 1 of the device, the second 37 additional current mirror, matched with second 17 power supply bus, third 38, fourth 39 and fifth 40 additional current mirrors, consistent with the first 13 power supply bus, first 41, second 42, third 43, fourth 44 and fifth 45 additional input field effect transistors with integrated gates that are connected to the first 7 bias voltage source, sixth 46, seventh 47, eighth 48, ninth 49 and tenth 50 additional input field effect transistors with integrated gates that are connected to the second 11 bias voltage source, the first 51 additional reference current source, eleventh 52 and twelfth 53 additional input field effect transistors, the sources of which are connected and connected to the second 17 the power supply bus through the second 54 additional reference current source, the third 55, fourth 56 and fifth 57 additional reference current sources, the thirteenth 58 and fourteenth 59 additional input field effect transistors, the sources of which are connected and connected to the second 17 power supply bus through the sixth 60 additional source reference current, the sources of the first 41 and sixth 46 additional input field effect transistors are connected to each other, the sources of the second 42 and seventh 47 additional input field effect transistors are connected to each other, the sources of the third 43 and eighth 48 additional input field effect transistors are connected to each other, the sources of the fourth 44 and ninth 49 additional input field effect transistors are connected to each other, the sources of the fifth 45 and tenth 50 additional input field effect transistors are connected to each other, the drains of the first 41, second 42, fourth 44 and fifth 45 additional input field effect transistors are connected to the second 17 bus power source, drains of the sixth 46, eighth 48, tenth 50 and eleventh 52 additional input field-effect transistors are connected to the first 13 bus of the power source, the first 32 output of the first 31 additional current mirrors is connected to the first 13 bus of the power source through the first 51 additional reference current source and connected to the combined sources of the first 41 and sixth 46 additional input field-effect transistors and the gate of the eleventh 52 additional input field-effect transistor, the second 33 output of the first 31 additional current mirrors is connected to the second 17 bus power supply through the third 55 additional reference current source and connected to the combined sources of the second 42 and seventh 47 additional input field-effect transistors and outputs of the third 38 and fifth 40 additional current mirrors, the third 34 output of the first 31 additional current mirrors is connected to the first 13 bus of the power source through the fourth 56 additional reference current source and connect it is connected to the combined sources of the second 5 and fourth 9 input field-effect transistors, the fourth 35 output of the first 31 additional current mirrors is connected to the input of the third 15 current mirrors, the fifth 36 output of the first 31 additional current mirrors is connected to the combined sources of the third 6 and sixth 10 input field-effect transistors, the drain of the twelfth 53 additional input field-effect transistor is connected to the input of the third 38 additional current mirror, the drains of the seventh 47 and ninth 49 additional input field effect transistors are connected to each other and connected to the input of the first 12 current mirror, the drain of the third 43 additional input field-effect transistor is connected to the input of the second 37 additional current mirrors, outputs of the fifth 20 current mirror and second 37 additional current mirrors are connected and connected to the combined sources of the fourth 44 and ninth 49 additional input field-effect transistors and the output of the fourth 39 additional current mirror stool, the output of the third 15 current mirror is connected to the combined sources of the third 43 and eighth 48 additional input field-effect transistors, the input of the fourth 39 additional current mirror is connected to the drain of the thirteenth 58 additional input field-effect transistor, the drains of the seventh 23 input field-effect transistor and the fourteenth 59 additional input field-effect transistor connected to each other and connected to the input of the fifth 40 additional current mirror, the second 19 output of the fourth 16 current mirror is connected to the first 13 bus of the power source through the fifth 57 additional reference current source and connected to the combined sources of the fifth 45 and tenth 50 additional input field-effect transistors and to the gate of the thirteenth 58th additional input field-effect transistor, the gate of the twelfth 53th additional input field-effect transistor is connected to the fourth 30 source of bias voltage, the gate of the fourteenth 59th additional input field-effect transistor connected to a third 29 bias voltage source.

Consider the work of the proposed scheme LE 2.

The truth table of the function y = x⊕i has the form:

x 0 1 2 0 1 2 0 1 2 i 0 1 2 y 0 1 2 1 2 0 2 0 1

Considering that x⊕2 = x⊖1, then for ternary variables the function y is written in the following form:

y = x⊕i = (x-2 (i> 0.5)) + ((x⊕1) -2 ((i <0.5) + (i> 1.5))) + ((x⊖ 1) -2 (i <1,5)), (1)

при i=0, переменная x⊕1 при i=1 и переменная x⊕2 (x⊖1) при i=2.Expression (1) is implemented by the circuit in FIG. 2, the variable gets to the output

for i = 0, the variable x⊕1 for i = 1 and the variable x⊕2 (x⊖1) for i = 2.

The input variable "x ₁ " in the form of an incoming current signal is supplied to the first 1 input of the device and then to the input of the first 31 additional current mirrors. The output signal from the first 32 output of the first 31 additional current mirrors is fed to the combined sources of the first 41 and sixth 46 additional input field effect transistors, and then to the gate of the eleventh 52 additional input field effect transistor, where the current of the first 51 additional source of reference current is subtracted from this signal. The operating modes of the first 41 and sixth 46 additional input field-effect transistors are set by the voltage values of the first 7 and second 11 bias voltage sources. The eleventh 52 and twelfth 53 additional input field-effect transistors form a DC, switching the drain currents of these transistors is determined by the signal supplied to the gate of the eleventh 52 additional input field-effect transistor. DC in this case serves as a threshold element by comparing a variable (x> 1.5) with a threshold level specified by the first 51 additional current sources. The choice of such a threshold level ensures independence of the signal conversion results from conversion errors within the current variation range of 0.5I ₀ . With a positive signal difference (x-1.5), the current of the second 54 additional source of reference current through the drain of the twelfth 53 additional input field-effect transistor is fed to the input of the third 38 additional current mirror. The output signal from the second 33 outputs of the first 31 additional current mirrors is added to the signal of the third 55 reference current source, and the output current of the third 38 additional current mirrors is subtracted from the resulting sum, forming the signal x⊕1. The input variable "i" in the form of an incoming current signal is supplied to the second 2 input of the device and then to the input of the fourth 16 current mirror. The output signal from the first 18 output of the fourth 16 current mirror is fed to the combined sources of the first 4 and fourth 8 input field-effect transistors, and then to the gate of the seventh 23 input field-effect transistor. The operating modes of the first 4 and fourth 8 input field-effect transistors are set by the voltage values of the first 7 and second 11 bias voltage sources. The seventh 23 and eighth 24 input field-effect transistors form a DC, switching the drain currents of these transistors is determined by the signal supplied to the gate of the seventh 23 input field-effect transistor. DC in this case performs the function of a threshold element by comparing a variable (i> 0.5) with a threshold level of the second 22 source of reference current. The choice of such a threshold level ensures independence of the signal conversion results from conversion errors within the current variation range of 0.5I ₀ . With a positive signal difference (i-0.5), the current of the third 25 source of the reference current through the drain of the eighth 24 input field-effect transistor is fed to the input of the second 14 current mirror. An “inhibit” signal is generated at the output of the second 14 current mirror, allowing the signal to be transmitted from the fifth 36 output of the first 31 additional current mirrors only at i = 0, thus forming the first term of expression (1). The output signal from the second 19 output of the fourth 16 current mirror is fed to the combined sources of the fifth 45 and tenth 50 additional input field effect transistors, and then to the gate of the thirteenth 58 additional input field effect transistor. The operating modes of the fifth 45 and tenth 8 additional are set by the voltage values of the first 7 and second 11 sources of bias voltage. The thirteenth 58 and fourteenth 59 additional input field-effect transistors form a DC, switching the drain currents of these transistors is determined by the signal supplied to the gate of the thirteenth 58 additional input field-effect transistor. DC in this case performs the function of a threshold element by comparing a variable (i <1.5) with a threshold level of the fifth 57 additional source of reference current. The choice of such a threshold level ensures independence of the signal conversion results from conversion errors within the current variation range of 0.5I ₀ . With a positive signal difference (i-1.5), the current of the sixth 60 additional source of reference current through the drain of the thirteenth 58 additional input field-effect transistor is fed to the input of the fourth 39 additional current mirror. At the output of the fourth 39 current mirror, an “inhibit” signal is generated, allowing the signal to be transmitted from the output of the second 37 additional current mirrors only at i = 2, thus forming the third term of expression (1). The output signal from the drain of the seventh 23 input field-effect transistor is added to the output signal from the drain of the fourteenth 59 additional input field-effect transistor and fed to the input of the fifth 40 additional current mirror. At the output of the fifth 40 current mirror, an “inhibit” signal is generated, allowing the transmission of the signal x⊕1 only at i = 1, thus forming the second term of expression (1). The output signal from the second 33 outputs of the first 31 additional current mirrors is added to the signal of the third 55 additional source of reference current and fed to the combined sources of the second 42 and seventh 47 additional input field effect transistors, where the currents from the outputs of the third 38 and fifth 40 additional current are subtracted from this signal mirrors. If the algebraic sum of these currents is positive through the drain of the seventh 47 additional input field-effect transistor, the current determined by the second term of expression (1) is fed to the input of the first 12 current mirror and then to the output of the logic element. The operating modes of the second 42 and seventh 47 additional input field-effect transistors are set by the voltage values of the first 7 and second 11 bias voltage sources. The output signal from the third 34 output of the first 31 additional current mirrors is fed to the combined sources of the second 5 and fifth 9 input field-effect transistors, and then to the gate of the ninth 26 input field-effect transistor, where the current of the fourth 56 additional auxiliary current source is subtracted from this signal. The operating modes of the second 5 and fifth 9 input field-effect transistors are set by the voltage values of the first 7 and second 11 bias voltage sources. The ninth 26 and tenth 27 input field-effect transistors form a DC, the switching of the drain currents of these transistors is determined by the signal fed to the gate of the ninth 26 input field-effect transistor. DC in this case performs the function of a threshold element by comparing a variable (x <0.5) with a threshold level of the fourth 56 additional source of reference current. The choice of such a threshold level ensures independence of the signal conversion results from conversion errors within the current variation range of 0.5I ₀ . With a positive signal difference (i-0.5), the current of the fourth 28 source of the reference current passes through the drain of the tenth 27 input field-effect transistor to the input of the fifth 20 current mirror. The signal from the output of the fifth 20 current mirror is summed with the output current of the second 37 additional current mirror, forming a signal x⊕2 = x⊖1, and together with the signal "ban" at the output of the fourth 39 additional current mirror through the drain of the ninth 49 additional input field-effect transistor to the input of the first 12 current mirror and then to the output of the logic element. The output signal from the fourth 35 outputs of the first 31 additional current mirrors is fed to the input of the third 15 current mirrors. The current of the first 21 current sources is subtracted from the signal from the output of the third 15 current mirror and supplied to the combined sources of the third 43 and eighth 48 additional input field-effect transistors. The operating modes of the third 43 and eighth 48 additional input field-effect transistors are set by the voltage values of the first 7 and second 11 bias voltage sources. The signal from the drain of the third 43 additional input field-effect transistor is fed to the input of the second 37 additional current mirror. The output signal from the fifth 36 output of the first 31 additional current mirrors is subtracted from the signal from the output of the second 14 current mirrors and fed to the combined sources of the third 6 and sixth 10 input field-effect transistors. The operating modes of the third 6 and sixth 10 input field-effect transistors are set by the voltage values of the first 7 and second 11 bias voltage sources. The signal from the drain of the sixth 10 input field-effect transistor is added to the signals from the drains of the seventh 47 and ninth 49 additional input field-effect transistors and fed to the input of the first 12 current mirror, where they are converted to the leakage current equal to them and transferred to the output of 3 devices.

In the circuit of FIG. 2 bipolar 61 is used to detect the presence of a quantum of current in the output circuit during experimental studies.

Shown in FIG. 4 simulation results confirm the indicated properties of the claimed scheme.

Thus, the considered circuit design of the current threshold element of the right cyclic shift is a necessary component of functionally complete bases, characterized by the multi-valued state of internal signals and signals at its current inputs and outputs, which can be the basis of computing and control devices using multi-valued linear algebra, private the case of which is Boolean algebra.

BIBLIOGRAPHIC LIST

1. Patent SU 1621164, 1991

2. Patent US 6.700.413, 2004

3. Patent US 6.414.519, 2002

4. Patent US 6.566.912, 2003.

5. Patent application US 2007/0018694, 2007

6. Patent application US 2004/0263210, 2004

7. Patent US 6.680.625, 2004

8. Patent US 5.742.154, 1998

9. Patent US 6.573.758, 2003.

10. Patent US 5.155.387, 1992

11. Patent US 4.713.790, 1987

12. Patent US 5.608.741, 1997

13. Patent US 4.185.210, fig. 2, 1980.

14. Patent US 3.040.192, fig. 1. 1962

15. Patent RU 2692573, 2019.

16. N.N. Prokopenko, N.V. Butyrlagin, N.I. Chernov, V.Ya. Yugai, “Basic Linear Elements of k-valued Digital Structures,” ICSES 2016 International Conference on Signals and Electronic Systems, Krakow, Poland, 5-7 September, 2016. pp. 7-12. DOI: 10.1109 / ICSES.2016.7847763.

17. N.N. Prokopenko, N.I. Chernov, V.Ya. Yugai, N.V. Butyrlagin. ”The Element Base of the Multivalued Threshold Logic for the Automation and Control Digital Devices,” on International Siberian Conference on Control and Communications, SIBCON-2017, Astana, Kazakhstan, June 29-30, 2017.

18. N.N. Prokopenko, N.I. Chernov, V.Ya. Yugai, N.V. Butyrlagin, “The Multifunctional Current Logical Element for Digital Computing Devices, Operating on the Principles of Linear (Not Boolean) Algebra,” IEEE East-West Design & Test Symposium (EWDTS’2016), Yerevan, Armenia, 14-17 Oct. 2016. pp. 278-282. DOI: 10.1109 / EWDTS.2016.7807723.

19. N.N. Prokopenko, N.I. Chernov, V.Ya. Yugai, P.S. Budyakov, “Logic functions representation and synthesis of k-valued digital circuits in linear algebra,” 2016 24nd Telecommunications Forum (TELFOR 2016), Belgrade, Serbia, November 22-23, 2016, pp. 1-4. DOI: 10.1109 / TELFOR.2016.7818892.

20. Chernov N.I. Fundamentals of the theory of the logical synthesis of digital structures over the field of real numbers // Monograph. - Taganrog: TRTU, 2001 .-- 147s.

21. Chernov N.I. Linear synthesis of digital structures ASOIU "// Textbook Taganrog. - TRTU, 2004, 118s.

Claims (1)

A current right cyclic shift threshold element comprising the first (1) and second (2) inputs of the device, the output (3) of the device, the first (4), the second (5) and the third (6) input field effect transistors connected to the gate the first (7) source of bias voltage, the fourth (8), fifth (9) and sixth (10) input field effect transistors of a different type of conductivity with integrated gates that are connected to the second (11) source of bias voltage, the sources of the first (4) and fourth (8) input field effect transistors are connected to each other, the sources of the second (5) and fifth (9) input field effect transistors are connected to each other, the sources of the third (6) and sixth (10) input field effect transistors are connected to each other, the first (12 ) a current mirror matched with the first (13) bus of the power source, the input of which is connected to the drain of the sixth (10) input field-effect transistor, the output of which is connected to the output (3) of the device, the second (14) current mirror, matched with the first (13 ) a power supply bus, the output of which is connected to the combined sources of the third (6) and sixth (10) input field-effect transistors, a third (15) current mirror, matched with the first (13) power source bus, and a fourth (16) current mirror, matched with a second (17) power supply bus containing the first (18) and second (19) outputs, the input of which is connected to the input (2) of the device, the fifth (20) current mirror, matched with the second (17) power supply bus, the output of the third ( 15) the current mirror is connected to the second (17) bus of the power source through the first (21) reference current source, the first (18) output of the fourth (16) current mirror is connected to the first (13) bus of the power source through the second (22) reference current source and connected to the combined sources of the first (4) and fourth (8) input field-effect transistors, the seventh (23) and eighth (24) input field-effect transistors, the sources of which are combined and connected to the second (17) power supply bus through a third (25) source oporno about current, the gate of the seventh (23) input field-effect transistor is connected to the combined sources of the first (4) and fourth (8) input field-effect transistors, the drain of the eighth (24) input field-effect transistor is connected to the input of the second (14) current mirror, ninth (26) and the tenth (27) input field effect transistors of a different type of conductivity, the sources of which are combined and connected to the first (13) bus of the power source through the fourth (28) reference current source, the drain of the tenth (27) input field effect transistor is connected to the input of the fifth (20) current mirrors, the gate of the ninth (26) input field effect transistor is connected to the combined sources of the second (5) and fifth (9) input field effect transistors, the drains of the first (4), second (5), third (6) and ninth (26) input field effect transistors connected to the second (17) bus of the power source, the drains of the fourth (8) and fifth (9) input field-effect transistors are connected to the first (13) bus of the power source, the third (29) bias voltage source is connected to the gate ru of the eighth (24) input field-effect transistor, the fourth (30) source of bias voltage is connected to the gate of the tenth (27) input field-effect transistor, characterized in that the first (31) additional current mirror, matched with the second (17) source bus, is introduced into the circuit power supply, containing the first (32), second (33), third (34), fourth (35) and fifth (36) outputs, the input of which is connected to the input (1) of the device, the second (37) additional current mirror, matched with the second (17) power supply bus, third (38), fourth (39) and fifth (40) additional current mirrors, consistent with the first (13) power supply bus, first (41), second (42), third (43), the fourth (44) and fifth (45) additional input field effect transistors with integrated gates that are connected to the first (7) bias voltage source, the sixth (46), seventh (47), eighth (48), ninth (49) and tenth ( 50) additional input field effect transistors with integrated gates, which connected to the second (11) bias voltage source, the first (51) additional reference current source, the eleventh (52) and twelfth (53) additional input field effect transistors, the sources of which are connected and connected to the second (17) bus of the power source through the second (54) ) an additional reference current source, the third (55), fourth (56) and fifth (57) additional reference current sources, the thirteenth (58) and fourteenth (59) additional input field-effect transistors, the sources of which are connected and connected to the second (17) bus the power source through the sixth (60) additional reference current source, the sources of the first (41) and sixth (46) additional input field effect transistors are connected to each other, the sources of the second (42) and seventh (47) additional input field effect transistors are connected to each other, the sources of the third (43) and eighth (48) additional input field effect transistors are connected to each other, the sources of the fourth (44) and ninth (49) additional input field effect transistors transistors are connected to each other, the sources of the fifth (45) and tenth (50) additional input field effect transistors are connected to each other, the drains of the first (41), second (42), fourth (44) and fifth (45) additional input field effect transistors are connected to the second (17) bus of the power source, the drains of the sixth (46), eighth (48), tenth (50) and eleventh (52) additional input field-effect transistors are connected to the first (13) bus of the power source, the first (32) output of the first ( 31) an additional current mirror is connected to the first (13) bus of the power source through the first (51) additional reference current source and is connected to the combined sources of the first (41) and sixth (46) additional input field effect transistors and the gate of the eleventh (52) additional input field field transistor, the second (33) output of the first (31) additional current mirror is connected to the second (17) bus of the power source through the third (55) additional reference current source and is connected to the combined sources of the second (42) and seventh (47) additional input field effect transistors and the outputs of the third (38) and fifth (40) additional current mirrors, the third (34) output of the first (31) additional current mirror is connected to the first (13) source bus power supply through the fourth (56) additional reference current source and is connected to the combined sources of the second (5) and fourth (9) input field-effect transistors, the fourth (35) output of the first (31) additional current mirror is connected to the input of the third (15) current mirror, the fifth (36) output of the first (31) additional current mirror is connected to the combined sources of the third (6) and sixth (10) input field effect transistors, the drain of the twelfth (53) additional input field effect transistor is connected to the input of the third (38) additional current mirror, drains the seventh (47) and ninth (49) additional input field-effect transistors are connected to each other and connected to the input of the first (12) current mirror, the drain of the third (4 3) an additional input field-effect transistor is connected to the input of the second (37) additional current mirror, the outputs of the fifth (20) current mirror and the second (37) additional current mirror are connected and connected to the combined sources of the fourth (44) and ninth (49) additional input field transistors and the output of the fourth (39) additional current mirror, the output of the third (15) current mirror is connected to the combined sources of the third (43) and eighth (48) additional input field effect transistors, the input of the fourth (39) additional current mirror is connected to the drain of the thirteenth (58 ) an additional input field effect transistor, drains of the seventh (23) input field effect transistor and fourteenth (59) additional input field effect transistor are connected to each other and connected to the input of the fifth (40) additional current mirror, the second (19) output of the fourth (16) current mirror connected to the first (13) bus of the power source through the fifth (57) additional the reference current source and is connected to the combined sources of the fifth (45) and tenth (50) additional input field effect transistors and to the gate of the thirteenth (58) additional input field effect transistor, the gate of the twelfth (53) additional input field effect transistor is connected to the fourth (30) voltage source bias, the gate of the fourteenth (59) additional input field-effect transistor is connected to a third (29) bias voltage source.

Images