RU2639579C2 - Method of manufacturing of powerful silicon shf ldmos transistors with modernized gate node of elementary cells - Google Patents

Method of manufacturing of powerful silicon shf ldmos transistors with modernized gate node of elementary cells Download PDF

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RU2639579C2
RU2639579C2 RU2016112149A RU2016112149A RU2639579C2 RU 2639579 C2 RU2639579 C2 RU 2639579C2 RU 2016112149 A RU2016112149 A RU 2016112149A RU 2016112149 A RU2016112149 A RU 2016112149A RU 2639579 C2 RU2639579 C2 RU 2639579C2
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Виктор Васильевич Бачурин
Станислав Михайлович Романовский
Ирина Петровна Семешина
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Акционерное общество "Научно-производственное предприятие "Пульсар"
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

FIELD: electricity.
SUBSTANCE: in the known method of manufacturing of powerful silicon SHF LDMOS transistors with a modernized gate node of elementary cells, including the creation of through source p+-bridges of elementary transistor cells in a high-resistance epitaxial p--layer of the initial silicon p-p+-substrate, growing of the gate dielectric on the front surface of the substrate, application of a layer of polysilicon on the gate dielectric and its phosphorus doping, application of a refractory metal to the polysilicon, the formation of a refractory metal polycide, the creation of the refractory metal from the polycide and the polysilicon layer located under it by the photolithography method of policide electrode of the gates of elementary cells in the form of narrow long longitudinal teeth of rectangular cross section, the creation in a high-resistance p--layer of the substrate of p-pockets, multistage lightly-doped n--drainage areas and high-alloyed n+-drainage areas and source of elementary cells by means of introduction, respectively, boron, phosphorus and arsenic ions into the substrate, when polycide electrode of the gate and photoresist layers are used as a protective mask and subsequent diffusion redistribution of impurities embedded in the substrate, a stepwise sedimentation of a multilevel intermediate dielectric onto the front surface of the substrate and a stepwise opening of contact windows over the high-alloyed p+-bridges, high-alloyed n+-drainage areas and source and pointwise over the polycide electrodes of the gate of elementary cells, the formation of multilevel metal drain electrodes and shunt buses of the gate, as well as the shielding electrodes of the elementary cells grounded at the source on the front surface of the substrate and the common metal electrode of the source of the transistor structure on its rear side, first create narrow polycidal longitudinal teeth of the gate node of the elementary cells and use them as a protective mask when introducing boron, phosphorus and arsenic ions into the substrate when forming respectively p-pockets, multistage lightly-doped n--drainage areas and high-alloyed n+-drainage areas and source of elementary cells, and metal conductors pointwise shunting the longitudinal polycarial gate teeth of the elementary cells form simultaneously with the 1st level of the shunt buses of the gate of the transistor structure over the through source p+-bridges in the high-resistance epitaxial p--layer of the substrate and from the same material.
EFFECT: more affordable and less expensive processing equipment for manufacturing.
7 dwg

Description

The invention relates to electronic semiconductor technology, in particular to methods for manufacturing high-power silicon microwave LDMOS (LateralDiffusedMetalOxideSemiconductor) transistors, and can be used to create a new generation of electronic equipment on their basis.

A known method of manufacturing a firm "Philips Semiconductors" a powerful silicon microwave LDMOS transistor 4th generation type BLF 2022-90 with a range of operating frequencies up to 2.0 ... 2.2 GHz and the level of power transferred to the load up to 90 W [1], selected as 1st analogue, including: the creation of through source p + jumper in a high resistance epitaxial p - layer of the original silicon p - p + substrate; growing gate dielectric with a thickness of 480

Figure 00000001
on the front surface of the p - layer of the substrate, applying a layer of polysilicon on the gate insulator and doping it with phosphorus; the formation of a polysilicon layer by photolithography of the gate electrode of the unit cells in the form of narrow (0.82 μm) longitudinal teeth of rectangular cross section with a length of 330 μm; creation in the high-resistance p - layer of the p-pocket substrate, three-stage lightly doped n - -regions of the drain and high-doped n + -regions of the drain and the source of unit cells by introducing boron, phosphorus and arsenic ions into the substrate, respectively, using a shutter polysilicon electrode as a protective mask and layers of photoresist and subsequent diffusion redistribution of impurities embedded in the substrate; deposition of a thick (0.8 ... 1.0 μm) interlayer dielectric on the front surface of the substrate and opening in it by photolithography of contact windows above the polysilicon gate teeth, source p + jumper wires and highly doped n + regions of the drain and the source of unit cells; the formation of metal screens, drain electrodes, source and shunt interlayers of polysilicon gate teeth of unit cells by photolithography from a three-layer coating Ti (0.08 μm) / TiW (0.14 μm) / Au (1.24 μm) on the front surface of the substrate and the total a metal electrode of the source of the transistor structure on its back side.

The main disadvantage of the 1st analogue method is that its implementation in industrial production due to the need to open narrow (0.25 ... 0.3 μm) long (330 μm) contact windows in a thick interlayer dielectric above polysilicon gate teeth of elementary cells and their subsequent shunting with gold plating requires expensive precision equipment and “exclusive” technological processes with submicron design standards that are absent in most potential manufacturers th devices of this class.

As the second analogue, a more affordable and less expensive method of manufacturing domestic high-power silicon microwave LDMOS transistors with an operating frequency f max = 2.0 GHz given to a pulsed load (t p = 100 μs, Q = 10) with a power of P output = 40 ... 45 W, power gain K ur = 11.5 ... 12 dB, efficiency of the drain circuit η с = 42 ... 45%, breakdown voltage of the drain pn junction U C. probe = 80 ... 85 V, percentage the yield of suitable structures on the plate is 42 ... 45%, in which [2]: the gate electrodes of the unit cells in the form of narrow (0.7 ... 0.72 μm) prot lined (340 μm) longitudinal teeth of rectangular cross section with a row (N ends = 13 pcs.) of branched contact pads adjacent to them from the source side with an optimal distance between them W open = 25 μm in relation to f max = 3.0 GHz created by the method of photolithography from a layer of polysilicon doped with phosphorus deposited on a gate dielectric with a specific surface resistance of the gate teeth ρ s.p.v. = 20 Ohm / □; in the high-resistance epitaxial p - layer of the initial silicon p - p + substrate before growing the gate insulator and forming p-pockets, additional local n + regions with a higher degree of doping were preliminarily formed under the branched contact pads of the gate teeth compared to later formed p -pockets; p-pockets, lightly doped three-stage n - regions of the drain, and highly doped n + regions of the drain and source were formed by introducing boron, phosphorus, and arsenic ions into the high-resistance p - layer of the substrate using polysilicon gate electrodes of unit cells and photoresist layers as a protective mask and subsequent high-temperature diffusion distillation, impurities embedded in the substrate; drain and source electrodes, shielding electrodes of elementary cells and buses, shunting polysilicon gate teeth of cells through branching contact pads adjacent to them were formed from an aluminum layer with addition of copper and silicon (AlCuSi) 2.0 ... 2.2 microns thick; the common metal electrode of the transistor structure was created from Ti (0.2 μm) / NiV (0.3 μm) / Ag (0.5 μm) after thinning the initial silicon substrate to a thickness of 120 ... 150 μm on its back side.

The main disadvantage of the second analogue is that it contains polysilicon electrodes of the gate of elementary cells and branch pads adjacent to them to reduce ρ zp are doped only with phosphorus, but are not additionally shunted by refractory metal silicides having an order of magnitude lower specific surface resistance (1,0 ... 2,5 Ohm / □). In particular, with ρ zpov = 1.0 Ohm / □, the thickness of the gate insulator d = 0.025 μm, W cell = 340 μm, f max = 3.0 GHz, the optimal distance between the tap-off contact areas of the gate can be increased to 110 μm, and the number of branched contact pads in each gate tooth should be reduced to 3, and as a result, the operating frequency range of the transistor structure should be raised to 3.6 ... 3.8 GHz and, in this case, K ur = 8.0 ... 10 dB.

As the third analogue, a method of manufacturing high-power silicon microwave microwave LDMOS transistors of the sixth and subsequent generations [3], which in the range of operating frequencies up to 3.6 GHz at a supply voltage of drain U s.pit = 28 V, is capable of delivering load power up to 150 W with a power gain K ur = 10 ... 14 dB and a efficiency of the drain circuit η s = 48 ... 55%. Such results were achieved due to: reduction of the minimum topological size of the transistor structure in comparison with the first analog from 0.35 μm to 0.14 μm; reducing the step of the unit transistor cell from 32.6 to 25 microns; reducing the value of the output capacity per unit length of the shutter 1.6 ... 2.0 times; reducing the width of polysilicon gate teeth of the cells from 0.82 microns to 0.3 ... 0.4 microns; the formation of local dielectric layers (“spacers”) on the lateral vertical faces of the polysilicon gate teeth of transistor cells and opening contact windows in a conformal dielectric coating on the front surface of the gate teeth; shunting of polysilicon gate teeth of cells with cobalt silicide (CoSi 2 ) instead of the gold coating Ti / TiW / Au; creating shielding electrodes of transistor cells from tungsten, and not from a gold coating Ti / TiW / Au; replacing acutely deficient and expensive two-level gold metallization with a more affordable and less expensive five-level aluminum-copper metallization in the formation of drain electrodes and the source of transistor cells and common drain and gate buses of the transistor structure; formation instead of a single-level thicker four-five-level interlayer dielectric on the front surface of the substrate.

The implementation of the above innovations imposes even more stringent requirements, compared with the first analogue, to the precision of the technological equipment used and the minimum topological dimensions of the transistor structure, which makes it possible to implement the third analogue with a yield rate of suitable structures on the plate acceptable for organizing cost-effective production of products for many potential manufacturers of devices of this class are extremely problematic. This is one of the main disadvantages of the 3rd analogue.

As a prototype, the method of creating domestic high-power silicon microwave LDMOS transistors [4], with breakdown voltage of the drain junction U s prob = 75 ... 80 V, the percentage of suitable crystals on the wafer 50 ... 52%, made on standard photolithographic equipment with minimal design with topological dimensions of 0.3 ... 0.4 μm, which at a frequency f = 3.1 GHz with a drain supply voltage U s.pit = 36 V gave pulsed (t p = 300 μs, Q = 10) power P o = 42 ... 45 W at the gain power ur K = 11 ... 14 dB and the ratio Runoff circuit efficiency η c = 42 ... 46%. Such results, compared with the essentially identical 2nd analogue method, were achieved due to the following improvements: additional shunting of phosphorus-doped polysilicon gate teeth of the unit cells with refractory metal branching pads adjacent to them from the source side; the formation of narrower (0.4 ... 0.45 μm) polycidic gate teeth of unit cells with a length of W cells = 340 μm with a smaller (3 pcs.) number of branch contact pads adjacent to the gate teeth from the source side and, accordingly, with a large optimal distance (W from = 110 μm) between them in each bolt; the introduction into the substrate through a gate dielectric of phosphorus ions with an energy of E = 60 ... 80 keV and a dose of D = 50 ... 60 μC / cm 2 and boron ions with E = 40 ... 60 keV and a dose of D = 3.0 ... 5.0 μC / cm 2 and subsequent diffusion distillation of impurities embedded in the substrate form highly doped local n + regions in the high-resistance p - layer of the substrate under the branched contact pads of the gate teeth and at the same time p-pockets of unit cells; formation instead of single-level in the 2nd method-analogue of a thicker multi-level interlayer dielectric and multi-level metal drain electrodes and metal shunt shutters above the through source p + jumper of unit cells in a high-resistance p - layer of the substrate.

The main disadvantage of the prototype method is the need for the formation of polycide gate teeth in it of unit cells with adjacent branch pads and additional local n + regions under branch contact pads, which seriously complicates the manufacturing process of transistor structures and reduces the yield of usable structures on plate and the deterioration of the frequency and energy parameters of the device.

The technical result of the present invention is the creation of a highly profitable basic process for manufacturing high-power silicon microwave LDMOST transistors with a frequency range of up to 3.0 ... 3.6 GHz using affordable domestic photolithographic equipment.

The technical result is achieved by the fact that:

1. In the known method of manufacturing high-power silicon microwave LDMOS transistors with a modernized gate unit of the unit cells, including the creation of through-source p + jumper unit transistor cells in a high-resistance epitaxial p - layer of the original silicon p - p + substrate, growing a gate dielectric surface of the substrate, applying a layer of polysilicon to the gate dielectric and doping it with phosphorus, applying polysilicon to a refractory metal, forming a polycide of a refractory metal and high-temperature polysilicon substrate surface annealing politsida creation of a refractory metal and located underneath the polysilicon layer by photolithography polycide gate electrodes of unit cells in the form of narrow elongated rectangular section longitudinal teeth, the creation of a high-resistance p - -layer substrate p-pockets multistage lightly doped n - -regions of runoff and highly doped n + -regions of runoff and the source of unit cells by introducing boron, phosphorus, and mouse ions into the substrate, respectively yak when used as a protective mask polycide gate electrodes and the resist layers and subsequent diffusion redistribution of impurities introduced into the substrate, the gradual deposition of multilevel interlayer dielectric on the front surface of the substrate and the gradual opening therein contact holes by photolithography over highly-p + -peremychkami, highly-n + -regions of the drain and source and pointwise above the polycide electrodes of the gate of the unit cells, the formation of multilevel metal drain electrodes and gate shunt buses, as well as elementary cells grounded to the source of the shield electrodes on the front surface of the substrate and a common metal electrode of the source of the transistor structure on its back side, first create narrow polycide longitudinal teeth of the gate assembly of the unit cells and use them as a protective mask for incorporation of boron, phosphorus, and arsenic ions into the substrate during the formation of p-pockets, multistage lightly doped n - regions of the drain, and highly doped n + regions of the drain and the source of the unit cells, and metal conductors that point-bypass the longitudinal polycidic gate teeth of the unit cells form simultaneously with the 1st level of the shunt bus bars of the transistor structure above the through source p + jumpers in the high-resistance epitaxial p - layer of the substrate and from the same material.

Comparative analysis with the prototype shows that the inventive method is characterized by the formation of narrow longitudinal polycide teeth of unit cells without branching contact pads adjacent to the gate teeth from the source side and using them as a protective mask when boron, phosphorus and arsenic ions are introduced into the substrate; in an alternative method of manufacturing microwave LDMOS transistors in accordance with paragraph 2 of the claims, narrow longitudinal teeth of elementary cells without branching contact pads adjacent to the gate teeth are created by photolithography from layers of polysilicon and refractory metal sequentially applied to the gate dielectric, and they are used as a protective mask for the introduction of boron, phosphorus, and arsenic ions into the substrate, and a polycrystalline refractory metal is formed on the surface of polysilicon at the stage of diffusion Onka impurities implanted into the substrate at an elevated temperature and in a particular environment; metal conductors, point-wise shunting the longitudinal teeth of the unit cells form simultaneously with the 1st level of the gate shunt buses above the through source p + jumpers in the high-resistance p - layer of the substrate and from the same material. Thus, the claimed method of manufacturing high-power silicon microwave LDMOS transistors meets the criteria of the invention of "novelty."

The process of forming a modernized gate assembly of elementary transistor cells proposed in the claimed method eliminates the need to create additional local n + -regions that are more highly doped compared to p-pockets and to implement a simplified technological route for manufacturing a transistor LDMOS structure with topological design standards comparable to the width of polycide gate electrodes unit cells.

In the present invention, the new combination, purpose and sequence of technological operations allows, in contrast to the prototype method, to create on a more affordable and less expensive technological equipment a more economical method of manufacturing high-power silicon microwave LDMOS transistors with a frequency range of up to 3.0 ... 3.6 GHz operating at supply voltages over a drain of more than 32 V with improved energy parameters, an increased percentage of suitable crystals on the wafer, that is, it exhibits howling technical properties. Therefore, the claimed method meets the criterion of "inventive step".

In figures 1 ... 7 shows the main stages of the manufacture of microwave LDMOS transistor structures with a modernized gate unit of elementary cells according to the claimed method, where the following notation is introduced:

1 - initial silicon p - p ++ substrate with high resistance epitaxial and high doped p-type layers;

2 - through source p + jumper of unit cells made of several autonomous units (2 1 , 2 2 , 2 3 ) in a high-resistance epitaxial p - layer of the substrate;

3 - gate dielectric;

4 - phosphorus doped polysilicon deposited on a gate dielectric;

5 - refractory metal deposited on polysilicon doped with phosphorus;

5 1 - polycide refractory metal formed on the surface of polysilicon;

6 - longitudinal polycide gate teeth of the unit cells, made by photolithography of a polycide of refractory metal and a layer of polysilicon located below it;

7 - a protective layer of photoresist;

8 - boron ions embedded in the substrate to create p-pockets of unit cells;

8 1 - p-pockets of unit cells formed by diffusion distillation of boron impurity embedded in the substrate;

9 - a protective layer of photoresist;

10, 11 — highly doped n + regions of the runoff and source of unit cells;

12 1,2,3,4 - multi-stage lightly doped n - -regions of runoff of unit cells;

13 - the first level of the interlayer dielectric;

14, 15 - the first level of the multilayer metal electrodes of the drain and the source of the unit cells;

16 - metal conductors shunting the longitudinal gate teeth of the unit cells;

17 - the second level of the interlayer dielectric;

18 - the second level of the metal electrodes of the drain of the unit cells;

19 - metal shielding electrodes of the unit cells;

20 - metal conductors connecting the shielding electrodes to the source electrodes of the unit cells;

21 is a common metal electrode of the source of the transistor structure on the back side of the substrate;

22 - induced n-channel, formed at the ends of the p-pockets adjacent to the gate dielectric (8 1 ) when a positive potential is applied to the gate electrode of the transistor structure.

Example

Based on the proposed method, samples were prepared of high-power silicon microwave LDMOS transistor structures (crystals) of 4.2 mm × 1.0 mm in size and with the length and total length of the induced n-channel of unit cells, respectively, L k = 0.38 ... 0.4 μm and W k = 95 mm, with a four-stage lightly doped n - region of the drain of transistor cells and a structure pitch of 26 μm, designed to operate in the frequency range up to 3.0 ... 3.6 GHz with drain supply voltages U s.pit = 28 ... 36 V. The source material for the manufacture of crystals as in the prototype method is silicon and p - p ++ -podlozhki oriented along the (100) plane, with the upper epitaxial vysokomnym p - -fiber thickness of 7.0 ... 7.5 mm and a resistivity ρ p = 10 ... 12 ohm-cm and lower high-alloy p ++ -layer with ρ p ++ = 0.005 Ohm⋅cm. For the manufacture of crystals, with the exception of several glasses, the same set of photomasks was used as in the prototype method.

The method is as follows:

1. The introduction of boron ions with an energy of 80 keV and a dose of 500 μC / cm 2 and the subsequent diffusion redistribution of the embedded impurity at a temperature of T = 1100 ° C in a nitrogen medium form through source p + jumper wires (2) of unit cells in the form of a number of autonomous cells blocks (2 1 , 2 2 , 2 3 ) in the high-resistance p - layer of the substrate with the optimal distance between them W from = 110 μm - Fig. 13.

2. Pyrogenic oxidation of silicon at T = 850 ° C is used to grow a gate insulator (3) with a thickness of 500 on the surface of the high-resistance epitaxial p - layer of the substrate

Figure 00000001
, a layer of polysilicon (4) 0.35 ... 0.4 μm thick is applied to the gate dielectric, doped with polysilicon phosphorus, sequentially precipitated onto a polysilicon layer of titanium and titanium nitride (5) with a thickness of 0.25 ... 0.3 μm each, high-temperature (T = 900 ° C) by annealing the silicon substrate in a nitrogen and hydrogen medium, titanium polycide (5 1 ) is formed on the surface of polysilicon (4) - FIG. one.

3. From the titanium polycide (5 1 ) and the polysilicon layer (4) located below it, the polycide gate electrodes of the unit cells (6) are created by photolithography in the form of narrow (0.4 ... 0.45 μm) longitudinal teeth of rectangular cross section

Figure 00000002
without branching contact pads adjacent to the gate teeth from the source side, the drain part of the transistor cells is covered with a protective layer of photoresist (7), boron ions (8) with an energy of E = 40 ... 60 keV and a dose of D = 3.0 ... 5, are embedded in the substrate 0 μC / cm 2 , the photoresist is removed from the front surface of the substrate and subsequent diffusion acceleration of boron impurities embedded in the substrate forms p-pockets (8 1 ) of transistor unit cells in the high-resistance p - layer of the substrate - Fig. 2, 3, 4.

4. By sequentially applying several photoresist protective layers on the front side of the substrate, opening the drain and source windows in each of them using photolithography, introducing arsenic and phosphorus ions into the substrate through open windows with certain energies and doses using shutter polycide electrodes (6) and layers photoresist (10) as a protective mask and subsequent joint diffusion distillation of impurities embedded in the substrate at elevated (900 ... 1000 ° C) temperature in a nitrogen environment create in a high-resistance p - layer under buckle high alloy n + -region drain (10) and source (11) and 4-stage weakly doped n - Photo-region (12 1,2,3,4) of elementary transistor cells - Fig. four.

5. The first level of the interlayer dielectric (13) is formed from a layer of borophosphorosilicate glass previously deposited on the front side of the substrate, in which contact windows are opened by photolithography over the highly doped n + regions of the drain (10) and source (11), the source p + - with jumpers (2, 2 1 , 2 2 , 2 3 ), apply AlCuSi metal coating 1.5 ... 2.5 μm thick on the interlayer dielectric (13) and create the first level of metal drain electrodes using photolithography method (14), source (15, 15 1 , 15 2 ) and shunt tires (16) of polycid gate teeth (6) elementary transistor cells - FIG. 5, 6.

6. The 2nd layer of borophosphorosilicate glass is deposited on the front side of the substrate (17), in which the contact windows are opened by photolithography above the 1st level of metal drain electrodes (14), source (15) and tires (16) shunting the polycidal gate teeth unit cells, a second layer of AlCuSi metal coating is applied on the front side of the substrate with a thickness of 1.0 ... 3.0 μm and a second level of metal drain electrodes (18) and shunt buses of polycidic gate teeth of cells (not shown in the figures) are formed by photolithography ), as well as the capping electrodes of transistor cells (19) connected to the source electrodes (15) by metal buses (20). A common metal electrode of the source of the transistor structure (21) on the back side of the substrate was created when the crystal was soldered to the heat sink surface of the case using a gold gasket, and the induced n-channel (22) was formed at the ends of the p-pockets (8 1 ) adjacent to the gate dielectric ( 3) when a positive voltage is applied to the gate electrode of the transistor structure - FIG. 7.

Crystals of microwave LDMOS transistors in accordance with the above technological route were made using standard photolithographic equipment with minimum design topological sizes of 0.3 ... 0.4 microns, exactly the same as in the prototype. The yield of suitable crystals on the plate was 56 ... 58% (in the prototype 50 ... 52%). Suitable crystals mounted in a KT-25 metal-ceramic case without beryllium ceramics had a breakdown voltage of the drain transition U s.probe = 75 ... 80 V and with a supply voltage across the drain U s.pit = 36 V in class AB mode, the pulse duration t p = 300 μs, duty cycle Q = 10, at a frequency f = 3.1 GHz, the power P out = 46 ... 48 W (in the prototype 42 ... 45 W) was given to the load with a power gain K ur = 14 ... 16 dB (in the prototype 11 ... 14 dB) and the efficiency of the drain circuit

η c = 47 ... 49% (in the prototype 42 ... 46%).

Approximately the same results were achieved in the manufacture of high-power silicon microwave LDMOS transistors according to claim 2. In this case, after growing the gate insulator on the front surface of the substrate, applying a layer of polysilicon on the gate insulator and doping it with phosphorus, sequentially depositing a titanium layer of titanium and titanium nitride (5) with a thickness of 0.25 ... 0.3 μm each, create a photolithography method from titanium and titanium nitride and a layer of polysilicon located below them, the gate electrodes of the unit cells (6) in the form of narrow (0.4 ... 0.45 μm) longitudinal teeth of rectangular cross section with a length of

Figure 00000003
without branching contact pads adjacent to the gate teeth from the source side and use them as a protective mask when boron, phosphorus and arsenic ions are introduced into the substrate, and titanium polycide on the polysilicon surface of the gate teeth of the unit cells is formed at the stage of diffusion acceleration of impurities embedded in the substrate with increased (900 ... 1000 ° С) temperature in the environment of nitrogen and hydrogen.

Comparing the above parameters with similar parameters of the prototype and other well-known foreign powerful silicon microwave LDMOS transistors having approximately the same structural and electrophysical parameters of the base crystal and designed for the same operating frequency range (3.0 ... 3.6 GHz) and pulsed to the load power (10 ... 120 W), we can draw the following conclusions:

1. The inventive method allows you to create powerful silicon microwave LDMOS transistors with the identical breakdown voltage of the drain junction (U s.probe = 75 ... 80 V), supply voltage across the drain (U s.pit = 36 V), but exceeding it: by 6, 0% yield of crystals on the plate; by 3.0 ... 4.0 W in terms of the level of impulse (t p = 300 μs, Q = 10) power supplied to the load; by 2.0 ... 3.0 dB in terms of power gain; by 3.0 ... 5.0% by the efficiency of the drain circuit and comparable with modern foreign analogues (BLF6G38-10, BLF6G3135-20, BLF6G38-25, BLS6G3135-120 from NXP, MRF7S35015HSR3, MRF7S35120HSR3 from Freescale Semiconduct330 IL30ELD, ILD IL5EL3, ILD, ILD530, ILD Integra Technologies) according to the main electrical parameters (P o , K ur , η s ).

2. The inventive method can significantly simplify the manufacturing process of high-power silicon microwave LDMOS transistors and more affordable and less expensive technological equipment to provide a high percentage of suitable structures on the plate, increase the range of products and reduce the cost of their manufacture.

The technical and economic efficiency of the proposed method consists in the possibility of creating and organizing a sustainable cost-effective industrial production of high-power silicon microwave LDMOS transistors with increased drain voltage, comparable with modern foreign analogues in energy parameters and designing electronic equipment based on them that meets modern and future requirements for performance characteristics, energy consumption, weight and size indicators, reliability and term with meadows.

Information sources

1. "Philips BLF2022-90 power MOSFET structural analysis." 3685 Richmond Road, Suite 500, Ottawa, ONK2H587, Canada, June 17, 2004 (analog).

2. RF patent for the invention No. 2473150 "High-power microwave LDMOS transistor and method for its manufacture", priority of the invention on August 17, 2011 (analog).

3. S.J.C.H. Theeuwen, H. Mollee "LDMOSTransistorsinPowerMicrowaveApplications", NXPSemiconductors, Gerstweg, 2.6534AE, Nijmegen, TheNetherlandssteven, theeuwen@nxp.com, hans.mollee@nxp.com (analogue).

4. RF patent for the invention No. 2535283 "Method for the manufacture of high-power silicon microwave LDMOS transistors", the priority of the invention June 26, 2013 (prototype).

Claims (1)

  1. A method of manufacturing high-power silicon microwave LDMOS transistors with a modernized gate unit of elementary cells, including the creation of through-source p + jumper of elementary transistor cells in a high-resistance epitaxial p - layer of the original silicon p - p + substrate, growing a gate dielectric on the front surface on a gate dielectric of a polysilicon layer and doping it with phosphorus, deposition of a refractory metal on polysilicon, formation of a refractory metal polycide on the surface olikremniya high temperature annealing of the substrate, the creation of politsida refractory metal and located underneath the polysilicon layer by photolithography polycide gate electrodes of unit cells in the form of narrow elongated rectangular section longitudinal teeth, the creation of a high-resistance p - -layer substrate p-pockets multistage lightly doped n - -regions Photo and high n + source and drain-regions of elementary cells by introducing into the substrate, respectively, boron ions, phosphorus and arsenic when one uses Hovhan as a protective mask polycide gate electrodes and the resist layers and subsequent diffusion redistribution of impurities introduced into the substrate, the gradual deposition of multilevel interlayer dielectric on the front surface of the substrate and the gradual opening therein contact holes by photolithography over -peremychkami highly-p +, n + highly--domains drain and source and point above the polycide electrodes of the gate of the unit cells, the formation of multilevel metal electrodes of gate shunt busbars, as well as elementary cells grounded to the source of the shielding electrodes on the front surface of the substrate and the common metal electrode of the source of the transistor structure on its back side, characterized in that they create narrow polycide longitudinal teeth of the gate unit cell unit and use them as protective mask when boron, phosphorus and arsenic ions are introduced into the substrate during the formation of p-pockets, multistage lightly doped n - -regions of the drain, and high - ligature, respectively of the n + -regions of the drain and the source of unit cells, and metal conductors that point-bypass the longitudinal polycidic gate teeth of the unit cells form simultaneously with the 1st level of the shunt buses of the gate of the transistor structure above the through source p + -throws in the high-resistance epitaxial p - layer of the substrate and from the same material.
RU2016112149A 2016-03-31 2016-03-31 Method of manufacturing of powerful silicon shf ldmos transistors with modernized gate node of elementary cells RU2639579C2 (en)

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