RU2535283C1 - Manufacturing method of high-power shf ldmos transistors - Google Patents

Abstract

FIELD: electricity.SUBSTANCE: in the manufacturing method of high-power SHF LDMOS transistors polysilicon applied to gate dielectric is coated with high-melting metal, by high-temperature annealing polycide of high-melting metal is formed at polysilicon surface, by photolithography from polycide of high-melting metal and polysilicon layer below it polycide gate teeth of elementary cells are formed with contact pads joining them from the source side and used as a blocking mask at introduction of boron, phosphorus and arsenic ions to the substrate while forming p-wells, multistage lightly doped n-areas of the drain and highly doped n+-areas of the drain and source of elementary cells, and accurate shunting of polycide gate cell teeth by metal bars is made through polycide branched contact pads joining gate teeth, at that in high-ohmic epitaxial p-layer of the substrate under branched contact pads of polysilicon gate teeth auxiliary local highly doped n+-areas are shaped with a higher doping degree in comparison with p-wells of elementary cells.EFFECT: invention provides development of modern basic nanotechnology for manufacturing of high-power SHF LDMOS transistors at more accessible and less expensive process equipment.7 dwg

Description

The invention relates to electronic semiconductor technology, in particular, to methods for manufacturing high-power silicon microwave LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, and can be used to create a new generation of electronic equipment on their basis.

A known method of manufacturing by Philips Semiconductors a high-power silicon microwave LDMOS transistor of the 4th generation type BLF 2022-90 with a range of operating frequencies up to 2.0 ... 2.2 GHz and the level of power transferred to the load up to 90 W [1], selected in as the first analogue, including: the creation of through source p ⁺ jumper wires in a high-resistance epitaxial p ^- layer of the initial silicon p ^- p ⁺ substrate; growing a gate dielectric with a thickness of 480 Å on the front surface of the p ^- layer of the substrate, applying a layer of polysilicon on the gate dielectric and doping it with phosphorus; the formation of a polysilicon layer by photolithography of the gate electrode of the unit cells in the form of narrow (0.82 μm) longitudinal teeth of rectangular cross section with a length of 330 μm; creation of p-pockets in the high-resistance p ^- layer, three-stage lightly doped n ^- -regions of the drain, and highly doped n ⁺ -regions of the drain and the source of unit cells by introducing boron, phosphorus, and arsenic ions into the substrate, respectively, using a shutter polysilicon electrode as a protective mask and layers of photoresist and subsequent diffusion redistribution of impurities embedded in the substrate; deposition of a thick (0.8 ... 1.0 μm) interlayer dielectric on the front surface of the substrate and opening in it by photolithography of contact windows above the polysilicon gate teeth, source p ⁺ jumper wires and highly doped n ⁺ regions of the drain and the source of unit cells; the formation of metal screens, drain electrodes, source and shunt interlayers of polysilicon gate teeth of unit cells by photolithography from a three-layer coating Ti (0.08 μm) / TiW (0.14 μm) / Au (1.24 μm) on the front surface of the substrate and the total a metal electrode of the source of the transistor structure on its back side.

The main disadvantage of the 1st analogue method is that it is implemented in industrial production because of the need to open narrow (0.25 ... 0.3 μm) long (330 μm) contact windows in a thick interlayer dielectric above the polysilicon gate teeth of the unit cells and their subsequent shunting with gold plating requires the availability of expensive precision technological equipment and “exclusive” technological processes with submicron design standards that are absent in most potential manufacturers of devices of this class.

As the second analogue, a more affordable and less expensive method of manufacturing domestic high-power silicon microwave LDMOS transistors [2] was chosen, in which: polysilicon electrodes of the gate of elementary transistor cells doped with phosphorus are made in the form of narrow (0.7 ... 0.72 μm ) extended (340 μm) longitudinal teeth of rectangular cross section with a number of branched contact pads adjacent to them from the source side; drain and source electrodes, shielding electrodes of unit cells and buses, shunting polysilicon gate teeth through branch pads adjacent to them are formed from an aluminum layer with copper and silicon additives (AlCuSi) 2.0 ... 2.2 microns thick; in the high-resistance epitaxial p ^- layer of the initial silicon p ^- p ⁺ substrate before growing the gate insulator on its front surface and forming p pockets, additional local n ⁺ regions with a higher degree of doping are preliminarily created under the branched contact areas of the gate teeth with later formed p-pockets; the optimal distance between the branch contact pads in each unit cell of the gate tooth and accordingly the number of branch contact pads are defined by the claims regulated [2] analytical relations W = _otv [k · d / (ρ _{s dressings max} · f)] ^1/2 (microns) and N _{kon.otv Cell #} = W / W _of (pieces) where the coefficient k = 1.47 × 10 ⁶ m / F, d - the thickness of the gate dielectric in microns, ρ _{of dressings} - surface resistivity in ohms of the gate teeth / □, W _cell - the length of the gate teeth of the cells in microns, · f _max - maximum working the frequency of the transistor LDMOS structure in GHz. Since the calculation shows that for a transistor structure with d = 0,025 mm, W = 340 microns _{Cell #,} ρ _s = _dressing 20 ohms / □, designed for operation in the frequency range f _max ≤3,0 GHz, the optimal distance between the branch gate pads and their number of teeth in each tooth of the bolt _holes must be W = 25 mm and N = _kon.otv 13 pcs. Such a large number of branch contacts gate pads due primarily high ρ _{of dressings} ~ 20 ohm / □, leads to a serious complication topology transistor structure, ascending structure pitch, a significant increase in its stray interelectrode capacitance of the gate-source and as a result, to reduce the number of crystals on the plate and reducing the percentage of yield of suitable crystals from the plate, a significant deterioration in the frequency and energy parameters of the device. Thus, the main disadvantage of the 2nd method-analog is that it polysilicon gate electrodes of the unit cells and the adjacent branched pads to reduce ρ _{of dressings} are doped only with phosphorus, but are not shunted further silicides of refractory metals having an order lower specific surface resistances (~ 1.0 ... 2.5 Ohm / □). In particular, for _dressing ρ _s = 1.0 ohm / □ and the above values of d = 0,025 mm, W = 340 microns _{Cell #,} f _max = 3.0 GHz, the optimal distance between the branch gate contact pads can be increased to 111 microns and reduce the number of branched contact pads in each gate tooth to 3 and, as a result, raise the operating frequency range of the transistor structure to 3.6 ... 3.8 GHz, and at the same time realize a power gain of at least 8.0 ... 10 dB.

A known method of manufacturing a firm "Ericsson Microelectronics" high-power silicon microwave LDMOS transistors, capable of a frequency of 2.14 GHz with a supply voltage across the drain U _s.pit = 28 V to give the load power up to 120 W with a power gain of K _ur = 13 dB designed to operate in cellular base stations in the frequency range 1.8 ... 2.0 GHz [3], selected as the third analogue, in which: metal drain electrodes of unit cells consist of 2 layers of gold - lower thickness 1.0 μm and the second upper 1.8 μm thick with a TiW / TiW (N) / TiW barrier sublayer in each of them; phosphorus-doped n ⁺ -siliconium gate teeth of transistor cells 0.6 μm wide, formed on a thin (500 Å) gate dielectric, includes a number of series-connected segments of a rectangular section of a specific length, shunted from above with a molybdenum polyoxide (MoSi ₂ ) 2500 Å thick with a specific surface resistance of 2.5 Ohm / □, and the polycide segments of the gate teeth, in turn, are point-bonded with solid metal tires formed by photolithography from the 2nd layer I have gold and placed on the upper surface of the two-level interlayer dielectric over the source p ⁺ -peremychkami unit cells; the shielding electrodes are made by photolithography from the lower (1st) layer of gold as a continuation of the source electrodes of the cells, while the shielding electrodes are located on the interlayer dielectric of the 1st level and completely surround the polycide gate teeth of the transistor cells around the periphery. With this design of the transistor LDMOS structure, the likelihood of additional short-circuits and leakage currents between the shielding electrodes and the polycide gate teeth of the unit cells increases sharply, which leads to a decrease in the yield of suitable crystals on the wafer and is one of the significant drawbacks of the third analogue.

The method of manufacturing high-power silicon microwave LDMOS transistors of the sixth and subsequent generations [4], which in the operating frequency range up to 3.6 GHz at a drain voltage of U _s.pit = 28 V, is capable of delivering up to 150 W with a power gain K _ur = 10 ... 14 dB and a drain circuit efficiency η _с = 48 ... 55%. Such results were achieved due to: reduction of the minimum topological size of the transistor structure in comparison with the first analog from 0.35 μm to 0.14 μm; reducing the step of the unit transistor cell from 32.6 to 25 microns; reducing the value of the output capacity per unit length of the shutter 1.6 ... 2.0 times; reducing the width of polysilicon gate teeth of the cells from 0.82 microns to 0.3 ... 0.4 microns; the formation of local dielectric layers (“spacers”) on the lateral vertical faces of the polysilicon gate teeth of transistor cells and opening contact windows in a conformal dielectric coating on the front surface of the gate teeth; shunting of polysilicon gate teeth of cells with cobalt silicide (CoSi ₂ ) instead of the gold coating Ti / TiW / Au; creating shielding electrodes of transistor cells from tungsten, and not from a gold coating Ti / TiW / Au; replacing acutely deficient and expensive two-level gold metallization with a more affordable and less expensive five-level aluminum-copper metallization in the formation of drain electrodes and the source of transistor cells and common drain and gate buses of the transistor structure; formation instead of a single-level thicker four-five-level interlayer dielectric on the front surface of the substrate.

The implementation of the above innovations imposes even more stringent requirements, compared with the first and third counterparts, for the precision of the used technological equipment and the minimum topological dimensions of the transistor structure, which makes it possible to implement the prototype method with a percentage of suitable structures on the plate acceptable for the organization of cost-effective production of products for many potential manufacturers of devices of this class are extremely problematic. This is one of the main disadvantages of the prototype.

The technical result of the present invention is the creation of modern basic nanotechnology for the manufacture of high-power silicon microwave LDMOS transistors with a frequency range of up to 3.0 ... 3.6 GHz on more affordable and less expensive technological equipment.

The technical result is achieved as follows.

1. In a known method for the manufacture of high-power silicon microwave LDMOS transistors, including the creation of through-source p ⁺ jumper elementary transistor cells in a high-resistance epitaxial p ^- layer of the original silicon p ^- p ⁺⁺ substrate, growing a gate dielectric on the front surface of the substrate, applying to gate dielectric of a polysilicon layer and doping it with phosphorus, formation of a gate of elementary cells in the form of narrow longitudinal teeth of rectangular cross section from a polysilicon layer by photolithography with a number of branched contact pads adjacent to them from the source side, creating p-pockets in the high-resistance p ^- layer, multi-stage lightly doped n ^- drain regions and highly doped drain n ⁺ regions and the source of unit cells by introducing boron ions into the substrate, respectively, phosphorus and arsenic when using a shutter polysilicon electrode and photoresist layers as a protective mask and the subsequent diffusion redistribution of impurities embedded in the substrate, phased deposition of multilevel of its interlayer dielectric on the front surface of the substrate and phased opening in it by the method of photolithography of the contact windows over the high doped p ⁺ jumper and source n ⁺ regions, polysilicon gate electrodes and high doped n ⁺ regions of the drain of unit cells, the formation of silicides and polysilicides of silicium metals and polysilicon in the opened windows, the formation of metal multilevel drain and source electrodes, grounded to the source of the shielding electrodes and metal buses, dot-shun polishing silicon polycide gate teeth of the transistor cells on the front surface of the substrate and the common metal electrode, the source of the transistor structure on its back side is coated with a polysilicon dielectric gate, a high-temperature annealing form a polycrystalline polysilicon on the surface of the polysilicon, photolithography method beneath it a layer of polysilicon polycid gate teeth of the unit cells adjacent to them with a hundred the source rons are branched contact pads and use them as a protective mask when boron, phosphorus and arsenic ions are introduced into the substrate during the formation of p-pockets, multistage lightly doped n ^- regions of the drain and highly doped n ⁺ regions of the drain and the source of unit cells, and the point shunting of polycide gate teeth of the cells with metal tires is carried out through polycid branch pads adjacent to the gate teeth, and in the high-resistance epitaxial p ^- layer The ligaments under the branched contact pads of the polysilicon gate teeth form additional local highly doped n ⁺ regions with a higher degree of doping as compared to the p-pockets of unit cells.

Comparative analysis with the prototype shows that the inventive method is different: the formation of a high-melting metal polyoxide by depositing a high-melting metal on the entire surface of the phosphorus-coated polysilicon layer and subsequent high-temperature annealing of the silicon substrate with high-melting metal in a certain medium at the stage of manufacture of the transistor structure regulated by the claims; the formation of polycidic gate teeth of the unit cells together with the branched contact pads adjacent to them on the source side by photolithography directly from polysilicon shunted by the refractory metal polycide, and not separately from polysilicon and subsequent bypassing of the already formed gate teeth by the refractory metal polycide, as is the case in the method prototype; the use of boron, phosphorus, and arsenic ions when introducing into the substrate, when creating p-pockets, lightly doped n ^- -regions of the drain and highly doped n ⁺ -regions of the drain and the source of the unit cells of polycidic, rather than polysilicon, gate electrodes; the formation of additional local n ⁺ -regions under the branched gate contact pads with the degree of doping regulated by the claims and at a certain stage of the manufacturing of the transistor structure. Thus, the claimed method of manufacturing high-power silicon microwave LDMOS transistors meets the criteria of the invention of "novelty."

The creation of the inventive method of polycide refractory metal on the entire surface deposited on the gate dielectric and phosphorus-doped polysilicon layer allows you to:

- to form the polycide gate teeth of the elementary transistor cells by photolithography directly from the polycide of the refractory metal and the layer of n ⁺ -silicon located below it;

- to exclude the process of formation of local dielectric interlayers (“spacers”) on the lateral vertical faces of the polysilicon gate electrodes or opening contact windows in the interlayer dielectric above narrow polysilicon gate teeth of the unit cells by photolithography, intended for subsequent shunting of polysilicon gate valves with metal alloys that are polysilicon place in the prototype and the 3rd analogue;

- to implement a simplified and more economical compared to the prototype technological route for manufacturing a transistor LDMOS structure on affordable and relatively inexpensive domestic technological equipment with topological design standards comparable to the width of the polycide gate electrode of the unit cells.

The formation in the inventive method under the branched contact pads of the gate electrodes of the elementary cells of additional local, more highly alloyed n ⁺ -regions in comparison with the p-pockets, created in contrast to the second analog after growing the gate dielectric and the formation of polysilicon gate electrodes, allows:

- to exclude the possibility of the acceptor impurity penetrating into the high-resistance p ^- layer of the substrate under the branched contact pads of the gate teeth of the cells during the formation of p-pockets;

- to provide an identical front for the advancement of acceptor and donor impurities under the polycide gate teeth of transistor cells along their entire length towards the drain and thus realize the same length of the induced n-channel along the entire length of the polycide gate teeth.

In addition, the formation in the claimed method of multi-stage lightly doped n ^- regions of unit cells instead of single-stage in the prototype method allows you to:

- to provide a more uniform distribution of the electric field in comparison with the prototype in multistage, lightly doped n ^- -regions of the drain with a reduced value of its intensity at the edges of n ^-- steps, directly adjacent to the high-doped n ⁺ -region of the drain and the p-pocket of unit cells;

- to realize the breakdown voltage of the drain p-n junction at the level of 75 ... 80 V and thus ensure the possibility of the transistor working at a supply voltage over the drain of more than 32 V, and therefore, ceteris paribus, increase the amount of power transferred to the load.

In the present invention, the new combination, purpose and sequence of technological operations allows, in contrast to the prototype method, to create on a more affordable and less expensive technological equipment a more economical method of manufacturing high-power silicon microwave LDMOS transistors with a frequency range of up to 3.0 ... 3.6 GHz operating at supply voltages above 32 V with improved energy parameters, an increased percentage of yield of suitable crystals on the wafer, that is, it shows a new technology physical property. Therefore, the claimed method meets the criterion of "inventive step".

In figures 1 ... 7 shows the main stages of the manufacture of microwave LDMOS transistor structures according to the claimed method, where the following notation is introduced:

1 - initial silicon p ^- p ⁺⁺ substrate with high-resistance epitaxial and highly doped p-type layers;

2 - through source p ⁺ jumper of elementary transistor cells made of several autonomous blocks (2 ₁ , 2 ₂ , 2 ₃ ...) in a high-resistance epitaxial p ^- layer of the substrate;

3 - gate dielectric;

4 - phosphorus-doped layer of polysilicon deposited on a gate insulator;

5 - refractory metal deposited on polysilicon (4);

5 ₁ - polycide refractory metal formed on the surface of polysilicon (4);

6 - polycide gate teeth of elementary transistor cells with branched contact pads adjacent to them from the source side (6 ₁ , 6 ₂ ), made by the method of photolithography from polycide refractory metal (5 ₁ ) and a layer of polysilicon located under it (4);

7 - a protective layer of photoresist;

8 - additional local highly doped n ⁺ -regions formed in the high-resistance p ^- -layer of the substrate under the branched contact pads (6 ₁ , 6 ₂ ) of the gate teeth of the unit cells;

9 - boron ions embedded in the substrate to create p-pockets of unit cells;

9 ₁ - p-pockets of unit cells formed by diffusion distillation of boron impurity embedded in the substrate;

10 - a protective layer of photoresist;

11, 12 - highly doped n ⁺ regions of the drain and source of elementary transistor cells;

13 _1,2,3,4 - multistage lightly doped n'-regions of elementary transistor cells;

14 - the first level of the interlayer dielectric;

15, 16 - the first level of the metal electrodes of the drain and the source of the elementary transistor cells;

17, 17 ₁ - the first level of shunting metal busbars of polycidic gate teeth of transistor cells;

18 - the second level of the interlayer dielectric;

19 - the second level of the metal electrodes of the drain of elementary transistor cells;

20 - metal shielding electrodes of elementary transistor cells;

21 - metal buses connecting the shielding electrodes to the source electrodes (16) of the transistor unit cells;

22 - a common metal electrode of the source of the transistor structure;

23 - induced n-channel, formed at the ends of p-pockets (9 ₁ ) of unit cells adjacent to the gate dielectric when applying a positive potential to the gate electrode of the unit transistor cells.

Example

Based on the proposed method, samples were prepared of high-power silicon n-channel microwave LDMOS transistor structures (crystals) of 4.2 mm × 1.0 mm in size with the total length and length (width) of the induced n-channel unit cells, respectively, L _k = 0.38 ... 0 , 4 μm and W _k = 95 mm, with a four-stage lightly doped n ^- region of the drain of transistor cells and a structure pitch of 26 μm, designed to operate in the frequency range up to 3.6 GHz with drain supply voltages U _s.pit = 28 ... 36 B. The starting material for the manufacture of crystals was silicon s p ^- p ⁺⁺ -podlozhki (1), oriented along the (100) plane, the upper high-resistance epitaxial p ^- -fiber thickness of 7.0 ... 7.5 mm and a resistivity ρ _p = 10 ... 12 ohm cm and lower highly doped p ⁺⁺ layer with ρ _{p ++} = 0.005 Ohm · cm.

The method is as follows.

1. The introduction of boron ions with an energy of 80 keV and a dose of 500 μC / cm ² and the subsequent diffusion redistribution of the embedded impurity at a temperature of T = 1100 ° C in nitrogen form through source p ⁺ jumpers (2, 2 ₁ , 2 ₂ , 2 ₃ ) unit cells in the high-resistance epitaxial p ^- layer of the substrate (1) - Figs. 1, 3.

2. Pyrogenic oxidation of silicon at T = 850 ° C is used to grow a gate insulator (3) with a thickness of 500 Å on the surface of a high-resistance epitaxial p ^- layer of the substrate, a polysilicon layer (4) with a thickness of 0.35 ... 0.4 μm is applied to the gate insulator, doped polysilicon phosphorus, sequentially deposited on a polysilicon layer of titanium and titanium nitride (5) with a thickness of 0.25 ... 0.3 μm each, by high-temperature (T = 900 ° C) annealing of the silicon substrate in a nitrogen and hydrogen medium, titanium polycide (5 ₁ ) is formed on the surface of polysilicon (4) - figure 1.

3. From the titanium polycide (5 ₁ ) and the polysilicon layer (4) located below it, the polycide gate electrodes of the unit cells (6) are created by photolithography in the form of narrow (0.4 ... 0.45 μm) rectangular longitudinal teeth with a length of W _cell = 340 μm with a number of branched contact pads adjacent to the gate teeth from the source side (6 ₁ , 6 ₂ ), with a distance between them in each gate tooth of the order of W _from = 110 μm, cover the drain part of the transistor cells with a protective layer of photoresist (7), introduce phosphorus ions with an energy of E = 60 ... 80 keV into the substrate dose of D = 50 ... 60 SCLC / cm ² of boron ions and (9) with E = 40 ... 60 keV, D = 3.0 and 5.0 ... SCLC / cm ^2, the photoresist is removed from the front surface of the substrate and subsequent diffusion embedded in distillation a substrate of impurities is formed in the high-resistance p ^- layer of the substrate by highly doped local n ⁺ regions (8) under the branched contact pads (6 ₁ , 6 ₂ ) of the gate teeth (6) and p-pockets (9 ₁ ) of the elementary transistor cells - figure 2 3.4.

4. By sequentially applying several photoresist protective layers on the front side of the substrate, opening the drain and source windows in each of them using photolithography, introducing arsenic and phosphorus ions into the substrate through open windows with certain energies and doses using shutter polycide electrodes (6) and layers photoresist (10) as a protective mask and the subsequent joint diffusion distillation of impurities embedded in the substrate at an elevated (900 ... 1000 ° C) temperature in a nitrogen environment create a high-resistance p ^- layer substrate ki high-doped n ⁺ -regions of the drain (11), source (12) and 4-step lightly doped n ^- -regions of the drain (13 _1,2,3,4 ) of the elementary transistor cells - figure 4.

5. The first level of the interlayer dielectric (14) is formed from the layer of borophosphorosilicate glass previously applied on the front side of the substrate, in which contact windows are opened by photolithography over the highly doped n ⁺ regions of the drain (11) and source (12), the source p ⁺ - with jumpers (2, 2 ₁ , 2 ₂ , 2 ₃ ) and branched contact pads (17) of the gate teeth of unit cells, an AlCuSi metal coating 1.5 ... 2.5 μm thick is applied to the interlayer dielectric (14) and created from it by photolithography 1st level metal electronic odov drain (15), a source (16, 16 _1, 16 ₂₎ and the shunt busbar (17, 17 ₁₎ polycide gate teeth (6) of elementary transistor cells - 5, 6.

6. A second layer of borophosphorosilicate glass is deposited on the front side of the substrate (18), in which contact windows are opened by photolithography above the first level of metal drain electrodes (15), source (16) and buses (17, 17 ₁ ), shunting polycidic gate teeth of elementary cells, a second layer of AlCuSi metal coating 1.0–3.0 μm thick is applied to the front side of the substrate and a second level of metal drain electrodes (19) and shunt busbars of polycidic gate teeth of cells (on figures not shown), but also shielding electrodes of transistor cells (20) connected to the source electrodes (16) by metal buses (21). A common metal electrode of the source of the transistor structure (22) on the back side of the substrate was created when the crystal was soldered to the heat sink surface of the case using a gold gasket, and the induced n-channel (23) was formed at the ends of p-pockets (9 ₁ ) adjacent to the gate dielectric ( 3) when applying a positive voltage to the gate electrode of the transistor structure - Fig.7.

Crystals of microwave LDMOS transistors in accordance with the above technological route were made using standard photolithographic equipment with minimum design topological sizes of 0.3 ... 0.4 μm, instead of 0.14 μm in the prototype. The yield of suitable crystals on the plate was 50 ... 52%. Suitable crystals mounted in the KT-25 metal-ceramic case without beryllium ceramics had a breakdown voltage of the drain junction U _sample = 75 ... 80 V and with a supply voltage across the drain U _sample = 36 V in class AB mode, pulse duration t _p = 300 μs, duty cycle Q = 10, at a frequency f = 3.1 GHz, the power P _out = 42 ... 45 W was transferred to the load with a power gain K _ur = 11 ... 14 dB and a drain coefficient η _s = 42 ... 46%

Comparing the above parameters with similar parameters of the prototype and other well-known foreign powerful silicon microwave LDMOS transistors having approximately the same structural and electrophysical parameters of the base crystal and designed for the same operating frequency range (3.0 ... 3.6 GHz) and pulsed to the load power (10 ... 120 W), we can draw the following conclusions.

1. The inventive method allows you to create powerful silicon microwave LDMOS transistors that are comparable with modern foreign counterparts in the main electrical parameters (P _o , K _ur , η _s ), but with higher (75 ... 78 V) compared with them breakdown voltage stock pn transition and, for this reason, capable of operating at drain supply voltages U _s.pit ≥36 V instead of U _s.pit = 28 ... 32 V for the prototype and analogues (BLF6G38-10, BLF6G3135-20, BLF6G38-25, BLS6G3135-120 of the company NXP, MRF7S35015HSR3, MRF7S35120HSR3 from Freescale Semiconductors, ILD3135M30, ILD3135EL20 from Integra Technologies) and others.

2. The inventive method can significantly simplify the manufacturing process of high-power silicon microwave LDMOS transistors and more affordable and less expensive technological equipment to provide a high percentage of suitable structures on the plate, increase the range of products and reduce the cost of their manufacture.

The technical and economic efficiency of the proposed method consists in the possibility of creating and organizing a sustainable cost-effective industrial production of high-power silicon microwave LDMOS transistors with increased drain voltage, comparable with modern foreign analogues in energy parameters and designing electronic equipment based on them that meets modern and future requirements for performance characteristics, energy consumption, weight and size indicators, reliability and term with meadows.

Information sources

1. "Philips BLF2022-90 power MOSFET structural analysis." 3685 Richmond Road, Suite 500, Ottawa, ONK2H587, Canada, June 17, 2004 (analog).

2. RF patent for the invention No. 2473150 "High-power microwave LDMOS transistor and method for its manufacture", priority of the invention on August 17, 2011 (analog).

3. A. Litwin, Q. Chen, J. Johansson, G. Ma, L-A. Olofsson, P. Perugupalli “High Power LDMOS technology for wireless infrastructure”, Ericsson Microelectronics, SE-16481 Kista, Sweden, Andrej Litwin@mic.ericsson.se Ericsson Microelectronics, Phoenix, AZ (analogue).

4. S.J.C.H. Theeuwen, H. Mollee “LDMOS Transistors in Power Microwave Applications”, NXP Semiconductors, Gerstweg, 2.6534AE, The Netherlands steven, theeuwen@nxp.com, hans.mollee@nxp.com (prototype).

Claims (1)

A method of manufacturing high-power silicon LDMOS microwave transistors, including the creation of through-source p ⁺ jumper wires of elementary transistor cells in a high-resistance epitaxial p ^- layer of the original silicon p ^- p ⁺⁺ substrate, growing a gate dielectric on the front surface of the substrate, applying a layer to the gate gate dielectric and doping it with phosphorus, forming from a polysilicon layer by the method of photolithography of the gate electrodes of elementary cells in the form of narrow longitudinal teeth of rectangular cross section with a number of adjacent constituents thereto from a source of branch contact pads, creating a high-resistance p ^- -layer substrate p-pockets multistage lightly doped n ^- -regions Photo and high n ⁺ source and drain-regions of elementary cells by introducing into the substrate, respectively, boron ions, phosphorus and arsenic when using a shutter polysilicon electrode and photoresist layers as a protective mask and subsequent diffusion redistribution of impurities embedded in the substrate, phased deposition of a multilevel interlayer dielectric on the front surface of the substrate and phased opening in it by photolithography of contact windows over the high-doped p ⁺ jumper and source n ⁺ -regions, polysilicon gate electrodes and high-doped n ⁺ -regions of the drain of unit cells, the formation of silicides and polycides of refractory metals polysilicon in the opened windows, the formation of metal multilevel drain and source electrodes, grounded to the source of the shielding electrodes and metal buses, point-shunting the floor the acidic gate teeth of the transistor cells on the front surface of the substrate and the common metal electrode, the source of the transistor structure on its back side, characterized in that the polysilicon deposited on the gate dielectric is coated with a refractory metal, high-temperature annealing form a refractory metal polycide on the surface of polysilicon, metal and a layer of polysilicon located beneath it, polycide gate teeth of the unit cells adjacent to them from the branched source pads and their use as a protective mask when introducing boron ions into the substrate, phosphorus and arsenic respectively when forming p-pockets multistage lightly doped n ^- -regions Photo and high n ⁺ source and drain-regions of elementary cells, and the point bypass of the polycide gate teeth of the cells with metal tires is carried out through the polycid branch pads adjacent to the gate teeth, moreover, in the high-resistance epitaxial p ^- -c Additional local highly doped n ⁺ regions with a higher doping level in comparison with p-pockets of unit cells form the substrate under the branched contact pads of polysilicon gate teeth.

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