WO2023082657A1

WO2023082657A1 - Method for preparing sic mosfet device

Info

Publication number: WO2023082657A1
Application number: PCT/CN2022/102319
Authority: WO
Inventors: 季益静; 吴贤勇; 刘峰松
Original assignee: 上海积塔半导体有限公司
Priority date: 2021-11-12
Filing date: 2022-06-29
Publication date: 2023-05-19
Also published as: CN114038757A; CN114038757B

Abstract

A method for preparing a SIC MOSFET device, comprising steps: providing a SIC substrate; forming, on the SIC substrate, well areas (13) of a first conductive type, first active areas (14) of the first conductive type, and second active areas (15) of a second conductive type that are arranged at intervals; forming a gate oxide layer (16) and a gate conductive layer (17) on the substrate surface or the substrate between the well areas (13); forming a gate dielectric layer (18) covering the gate conductive layer (17); forming a first active area metal layer (23) and a second active area metal layer (24); and annealing the first active area metal layer (23) and the second active area metal layer (24) at different temperatures to respectively form a first ohmic contact and a second ohmic contact. When the SIC MOSFET device is prepared, different annealing temperatures are used when an N-type area metal layer and a P-type area metal layer are annealed, such that an N-type area and a P-type area can be annealed at different optimal annealing temperatures, and a P-type ohmic contact area and an N-type ohmic contact area both can get optimal contact resistivity, thereby facilitating improvement in performances of the device.

Description

Fabrication method of SIC MOSFET device

technical field

The invention relates to the field of power devices, in particular to a method for preparing a SIC MOSFET device.

Background technique

Since MOSFET devices are unipolar devices, there are no minority carriers participating in conduction, so the high-frequency characteristics are superior. However, silicon-based MOSFETs are limited by the design formula Rdson∝VB ² of unipolar devices, and the on-resistance is very low when making high-voltage devices. Therefore, the voltage level of common high-voltage silicon-based MOSFET devices on the market is generally several hundred volts. The current mainstream high-voltage switching tube is silicon-based IGBT, but due to the introduction of bipolar conductance modulation, the switching frequency is greatly limited.

High-voltage silicon carbide MOSFET devices have low on-resistance due to their wide bandgap and high-voltage-resistant materials, so they have attracted more and more attention from the market in recent years. They are used in electric vehicle inverters, charging piles, and uninterruptible power supplies. and other fields have been used more and more. However, due to the characteristics of the material itself, the manufacturing process of silicon carbide semiconductor devices is different from the traditional silicon process in many aspects, and it is more complicated and difficult. In the SIC MOSFET source manufacturing process, the P-type source and the N-type source are short-circuited, and in order to simplify the process flow, the P-type source and the N-type source are formed at the same time in the same process, and at the same time in the rapid annealing furnace rapid annealing at the same temperature. Existing process methods often need to compromise the contact resistivity of P-type and N-type sources, that is to say, the N-type contact and P-type contact of the final product are not the lowest contact resistivity that can be achieved respectively. The inventors have found through a lot of research that since N-type silicon carbide requires an ohmic contact annealing temperature close to 1000°C, and for P-type silicon carbide, the optimal annealing temperature is relatively low, only 800°C-900°C, so in the prior art In the preparation of SIC MOSFET devices, the method of annealing the P-type source and the N-type source in the annealing furnace at the same time cannot form a good P-type and N-type source ohmic contact at the same time, resulting in at least one of them having a high resistivity. A higher N-type source contact resistivity will lead to an increase in the forward conduction resistance, and a higher P-type source contact resistivity will affect its conduction performance when the MOSFET reverse body diode is turned on. For this reason, the inventor has proposed a kind of improvement scheme through long-term research.

Contents of the invention

In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of preparation method of SIC MOSFET device, be used to solve when preparing SIC MOSFET device in the prior art, P-type source and N-type source are in the same Formed at the same time in the process, and rapid annealing at the same temperature in the rapid annealing furnace, it is impossible to form good P-type and N-type source ohmic contacts at the same time, resulting in problems such as degradation of device performance.

In order to achieve the above-mentioned purpose and other related purposes, the invention provides a kind of preparation method of SIC MOSFET device, described preparation method comprises steps:

A SIC substrate is provided, and a plurality of well regions of the first conductivity type arranged at intervals, a first active region of the first conductivity type and a second active region of the second conductivity type located in the well regions are formed in the SIC substrate. region, the second active region is adjacent to the opposite sides of the first active region, the first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type type;

forming a gate oxide layer and a gate conductive layer on the surface of the substrate between the well regions or in the substrate, and forming a gate dielectric layer covering the gate conductive layer to obtain a gate structure;

forming a first active area metal layer and a second active area metal layer, the first active area metal layer is located on the surface of the first active area and is in contact with the first active area, the second active area The region metal layer is located on the surface of the second active region and is in contact with the second active region;

Annealing is performed on the first metal layer in the active area and the metal layer in the second active area at different temperatures to form a first ohmic contact and a second ohmic contact respectively.

Optionally, a plurality of well regions of the first conductivity type arranged at intervals, a first active region of the first conductivity type and a second active region of the second conductivity type located in the well regions are formed in the SIC substrate. The district process consists of steps:

Forming a first mask layer on the SIC substrate, the pattern of the well region is defined on the first mask layer, and under the action of the first mask layer, the first conductivity type is carried out on the SIC substrate. ion implantation to form a plurality of well regions of the first conductivity type spaced apart in the SIC substrate;

Forming a second mask layer on the SIC substrate, the second mask layer defines the pattern of the second active region, under the action of the first mask layer and the second mask layer, the Ion implantation of the second conductivity type is performed in the well region, so as to form a plurality of the second active regions distributed at intervals in the well region;

A third mask layer is formed on the SIC substrate, the pattern of the first active region is defined on the third mask layer, and the first conduction is performed on the well region under the function of the third mask layer. type ion implantation to form the first active region in the well region;

Remove the remaining masking layer.

Optionally, after removing the remaining mask layer, a step of performing high-temperature annealing on the obtained structure to activate implanted ions and repair implanted damage is also included.

More optionally, the high-temperature annealing is performed on furnace tube equipment, and the annealing temperature is greater than or equal to 800°C.

Optionally, the preparation method further includes the step of forming a plurality of extraction electrodes and a drain ohmic contact after the ohmic contact is formed, the plurality of extraction electrodes are connected to the first active region metal layer, the second active area metal layer, and the second active area respectively. The region metal layer is electrically connected to the gate structure; the drain ohmic contact is located on the surface of the SIC substrate away from the gate structure.

Optionally, the first metal layer in the active area is connected to the second metal layer in the active area, and are formed synchronously in the same process.

Optionally, the material of the first metal layer in the active area and the metal layer in the second active area includes nickel.

Optionally, the step of annealing the first active-region metal layer and the second active-region metal layer to respectively form the first ohmic contact and the second ohmic contact includes:

A protective layer is formed on the surface of the structure obtained after forming the first active area metal layer and the second active area metal layer, and the protective layer covers the P-type active area in the first active area and the second active area. district;

Simultaneous annealing is performed on the first active region and the second active region by laser annealing, wherein the actual annealing temperature of the P-type active region covered with the protective layer is lower than that of the first active region not covered with the protective layer and the actual annealing temperature of the N-type active region in the second active region.

More optionally, the actual annealing temperature of the P-type active region is 800°C-900°C, and the actual annealing temperature of the N-type active region is 1000°C-1200°C.

Optionally, the material of the first mask layer, the second mask layer and the third mask layer includes a silicon oxide layer and/or a polysilicon layer.

Optionally, the protective layer includes a titanium nitride layer and/or a silicon nitride layer.

As mentioned above, the preparation method of the SIC MOSFET device of the present invention has the following beneficial effects: the present invention adopts different annealing temperatures for the metal layer of the N-type region and the metal layer of the P-type region in the process of preparing the SIC MOSFET device, and, The present invention proposes to form a protective layer on the surface of the P-type active region in the first active region and the second active region before annealing, and then carry out laser annealing synchronously, using the principle that the laser action temperature decreases with the increase of depth, so that the annealing In the process, the laser directly acts on the N-type region, and the actual annealing temperature of the P-type active region covered with a protective layer is lower than that of the N-type active region in the first active region and the second active region not covered with a protective layer. The actual annealing temperature of the active region enables the N-type region and the P-type region to be annealed at different optimal annealing temperatures, so that both the P-type ohmic contact region and the N-type ohmic contact region can obtain the optimal contact resistivity. help improve device performance.

Description of drawings

Fig. 1 shows the schematic diagram of the cross-sectional structure when the well region of the first conductivity type is prepared for the preparation method of the SIC MOSFET device provided by the present invention.

Fig. 2 shows the cross-sectional structure schematic diagram when preparing the second active region for the preparation method of the SIC MOSFET device provided by the present invention.

FIG. 3 shows a schematic cross-sectional structure diagram of the preparation method of the SIC MOSFET device provided by the present invention when preparing the first active region.

Fig. 4 shows the schematic diagram of the cross-sectional structure after the preparation of the first active region and the second active region is completed for the preparation method of the SIC MOSFET device provided by the present invention.

FIG. 5 shows a schematic cross-sectional structure diagram of preparing a gate oxide layer for the preparation method of the SIC MOSFET device provided by the present invention.

Fig. 6 shows a schematic cross-sectional structure diagram of preparing a gate conductive layer for the preparation method of the SIC MOSFET device provided by the present invention.

Fig. 7 shows a schematic cross-sectional structure diagram of preparing the first active region metal layer and the second active region metal layer for the preparation method of the SIC MOSFET device provided by the present invention.

Fig. 8 shows a schematic diagram of the cross-sectional structure of the ohmic contact prepared by the preparation method of the SIC MOSFET device provided by the present invention.

Fig. 9 shows a schematic diagram of the cross-sectional structure of the preparation method of the SIC MOSFET device provided by the present invention and the preparation of the lead-out electrode and the drain ohmic contact.

Component designation description

11-SIC substrate; 12-SIC epitaxial layer; 13-well region; 14-first active region; 15-second active region; 16-gate oxide layer; 17-gate conductive layer; 18-gate dielectric layer ; 19-first mask layer; 20-second mask layer; 21-third mask layer; 22-protective layer;

23-first active metal layer; 24-second active metal layer; 25-extraction electrode; 26-drain ohmic contact; 27-JFET region.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated. In order to make the illustrations as concise as possible, not all structures are marked in each drawing.

In the manufacturing process of the SIC MOSFET device in the prior art, the P-type source and the N-type source are simultaneously formed in the same process, and the rapid annealing at the same temperature is carried out in the rapid annealing furnace at the same time. Existing process methods often need to compromise the contact resistivity of P-type and N-type sources, that is to say, the N-type contact and P-type contact of the final product are not the lowest contact resistivity that can be achieved respectively. The inventors have found through a lot of research that since N-type silicon carbide requires an ohmic contact annealing temperature close to 1000°C, and for P-type silicon carbide, the optimal annealing temperature is relatively low, only 800°C-900°C, so in the prior art When preparing SIC MOSFET devices, the method of annealing the P-type source and the N-type source in the annealing furnace at the same time leads to a high resistivity of at least one of them, and the higher contact resistivity of the N-type source will lead to forward conductivity. The on-resistance increases, and the higher P-type source contact resistivity affects its conduction performance when the MOSFET reverse body diode is turned on. For this reason, the inventor has proposed a kind of improvement scheme through long-term research.

Specifically, as shown in Figures 1 to 9, the present invention provides a preparation method of a SIC MOSFET device, the preparation method comprising steps:

A SIC substrate is provided, and a plurality of well regions 13 of the first conductivity type are formed at intervals in the SIC substrate, and a first active region 14 of the first conductivity type and a first active region 14 of the second conductivity type located in the well regions 13 are provided. Two active regions 15, the second active region 15 is adjacent to opposite sides of the first active region 14 (that is, the first active region and the second active region 15 are in contact with each other), the first conductivity type is N type and the second active region The second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type; the SIC substrate may specifically include a SIC substrate layer 11 (ie, a SIC wafer) and a SIC located on the SIC substrate layer 11. The epitaxial layer 12, in other examples, may also include a SIC buffer layer located between the SIC substrate layer 11 and the SIC epitaxial layer 12. The SIC epitaxial layer 12 may be formed by an epitaxial process, and the subsequently formed well region 13 and other structures are all It is formed in the SIC epitaxial layer, and the bottom of each structure preferably has a distance from the bottom of the SIC epitaxial layer 12, or the height of each structure formed subsequently is smaller than the height of the SIC epitaxial layer 12, and the SIC spaced between the well regions 13 The base region is called JFET region 27 (junction field effect transistor region), the edge of the second active region 15 and the edge of the well region 13 have intervals, and the bottom of the first active region 14 and the second active region 15 There is usually also a space from the bottom of the well region 13, and the distance between the first active region 14 and the second active region 15 and the edge of the well region 13 is the channel region of the device. The process can be specifically shown in Figures 1-4;

A gate oxide layer 16 and a gate conductive layer 17 are formed on the surface of the substrate between the well regions 13 or in the substrate, and a gate dielectric layer 18 covering the gate conductive layer 17 is formed to obtain a gate structure, and the gate structure extends to the The entire surface of the well region 13, and extends to a part of the surface of the second active region 15; the gate structure can be a planar gate, and its formation process can be shown in FIG. 5 and FIG. The gate oxide layer 16, the gate conductive layer 17 and the gate dielectric layer 18, the formation process of the gate oxide layer 16 is preferably but not limited to thermal oxidation, the gate conductive layer 17 is preferably but not limited to a polysilicon layer, and the formation method includes but not limited to vapor deposition The material of the gate dielectric layer 18 can be formed by SiO2, BPSG, SiN and other formation processes including but not limited to vapor deposition processes; the gate structure can also be a trench gate, and the specific type of the gate structure is not limited in this embodiment. However, it will mainly be illustrated with a planar gate structure;

Forming a first active region metal layer 23 and a second active region metal layer 24, the first active region metal layer 23 is located on the surface of the first active region 14 and is in contact with the first active region 14, so The second active area metal layer 24 is located on the surface of the second active area 15 and is in contact with the second active area 15; the first active area metal layer 23 and the second active area metal layer 24 can be mutually Connection, the two can be formed in the same process, such as by the same sputtering process, and the materials of the two include but are not limited to metals such as nickel, copper, aluminum; the structure obtained after this step is shown in Figure 7;

Annealing the first active-region metal layer 23 and the second active-region metal layer 24 at different temperatures to form the first ohmic contact and the second ohmic contact respectively, the two annealing may be performed in different annealing processes and can use furnace tube annealing or other annealing processes, but in a preferred example, the process is:

A protection layer 22 is formed on the surface of the structure obtained after forming the first active region metal layer 23 and the second active region metal layer 24, the protection layer 22 includes but not limited to a silicon nitride layer and/or a titanium nitride layer, The thickness of the protective layer 22 is different according to the material of the first active area metal layer 23 and the second active area metal layer 24 and/or the specific material of the protective layer 22. For example, in an example, the protective layer Layer 22 is a titanium nitride layer with a thickness of more than 300 angstroms, but preferably less than 2000 angstroms. The protective layer 22 covers the P-type active region 14 and the second active region 15. Active region, that is, when the first active region 14 is a P-type region, then cover the first active region 14, otherwise cover the second active region 15, the structure obtained in this step is as shown in Figure 8, the dotted line in Figure 8 The actual annealing temperatures at the two positions at the box marks are different;

Synchronous annealing is performed on the first active region 14 and the second active region 15 by laser annealing, wherein the actual annealing temperature of the P-type active region covered with the protective layer 22 is lower than that of the first active region not covered with the protective layer 22 The actual annealing temperature of the N-type active region in the second active region 15 . The principle is that laser rapid annealing uses laser beams to irradiate the semiconductor surface, which generates extremely high temperatures in the irradiated area, but the depth of the high temperature effect is shallow. As the depth increases, the temperature decreases, while the SiC MOSFET source ohmic contact is prepared. , the optimal annealing temperature of P-type and N-type is different, and the optimal annealing temperature of P-type is lower than that of N-type. The source is subjected to ohmic contact annealing, and the presence of the P-type protective layer 22 makes its ohmic contact annealing temperature relatively low, while the laser directly acts on the N-type region, and its ohmic contact annealing temperature is relatively high, thereby simultaneously obtaining optimal contact resistivity . Taking nickel metal as an example, compare the ohmic contact resistivity data formed by SiC with different doping types as shown in the table below:

Table 1 Resistivity difference of different annealing methods

In Table 1, RTA rapid annealing is the simultaneous annealing of the P-type source and the N-type source in the annealing furnace sink using the prior art, and laser annealing (there is a protective layer in the P region) means that the design of the P-type source using the example of the present invention is adopted. Protected and laser annealed. It can be seen from Table 1 that the P region is provided with a protective layer and laser annealing is used to improve the contact resistivity of the P region, so that both the P-type region and the N-type region can obtain optimal contact resistivity.

The application adopts different annealing temperatures for the P-region and the N-region, which can make the P-type region and the N-type region obtain optimal resistivity, which helps to improve device performance, and in a further preferred solution, the annealing of the two The process is carried out synchronously, which helps to simplify the manufacturing process, and at the same time prevents the device from being damaged after multiple annealings. Of course, if the protective layer 22 is a non-conductive layer, the protective layer 22 needs to be removed after the ohmic contact is formed. However, if the formed protective layer 22 is a metal layer, it does not need to be removed.

In an example, a plurality of well regions 13 of the first conductivity type arranged at intervals, a first active region 14 of the first conductivity type located in the well regions 13 and a first active region of the second conductivity type are formed in the SIC substrate. The process of the second active region 15 comprises the steps of:

A first mask layer 19 is formed on the SIC substrate, the pattern of the well region 13 is defined on the first mask layer 19, and the first mask layer 19 is used to perform the first mask layer on the SIC substrate. Ion implantation of a conductivity type to form a plurality of well regions 13 of the first conductivity type at intervals in the SIC substrate; for example, if the first conductivity type is P-type, aluminum or boron ions can be implanted, if the first If the conductivity type is N-type, nitrogen, phosphorus or arsenic ions can be implanted. The specific implantation parameters can refer to the conventional parameters in this field, which are not limited in this embodiment, but the well region 13 is usually lightly doped; the first mask The film layer 19 includes but is not limited to a silicon oxide layer, that is, a layer of SiO ₂ with a thickness of 0.5-3um is first grown, and then a photoresist layer is formed by a coating process, and then exposed and developed to define the desired pattern. The photoresist is used as the The mask is subjected to _SiO2 dry etching, the structure obtained after this step is shown in Figure 1, it can be seen that the remaining first mask layer 19 is correspondingly located above the JFET region 27;

A second mask layer 20 is formed on the SIC substrate, the second mask layer 20 defines the pattern of the second active region 15, and the first mask layer 19 and the second mask layer 20 The ion implantation of the second conductivity type is performed on the well region 13 under the action, so as to form a plurality of the second active regions 15 distributed at intervals in the well region 13; the second mask layer 20 is also preferably Silicon oxide layer, which together with the remaining first mask layer 19 constitutes the barrier layer in this step, the structure obtained after this step is shown in Figure 2; after this step, the remaining first mask layer 19 and the first mask layer 19 can be removed Second mask layer 20;

A third mask layer 21 is formed on the SIC substrate, the pattern of the first active region 14 is defined on the third mask layer 21, and the effect of the third mask layer 21 on the well region 13 perform ion implantation of the first conductivity type to form the first active region 14 in the well region 13; the third mask layer 21 is also preferably a silicon oxide layer, the first active region 14 and the second The second active region 15 is usually heavily doped, so the doping concentration of the first active region 14 is usually greater than the doping concentration of the well region 13; the structure obtained after this step is shown in Figure 3;

The remaining mask layer is removed, and the resulting structure is shown in FIG. 4 .

In one example, after removing the remaining mask layer, a step of performing high temperature annealing on the obtained structure to activate implanted ions and repair implanted damage is further included. The high-temperature annealing in this step is preferably performed on furnace tube equipment, and the annealing temperature is greater than or equal to 800°C.

In one example, the preparation method further includes the step of forming a plurality of extraction electrodes 25 and a drain ohmic contact 26 after forming the ohmic contacts, the plurality of extraction electrodes 25 are respectively connected to the first active region metal layer 23 , the second active region metal layer 24 is electrically connected to the gate structure; the drain ohmic contact 26 is located on the surface of the SIC substrate away from the gate structure (ie the back side of the SIC substrate). The material of the extraction electrode 25 includes but not limited to metal materials such as gold and silver, and the formation method includes but not limited to the sputtering method. The contact holes of layer 17 are then sputter-deposited on the contact holes; the structure obtained after this step is shown in FIG. 9 .

In a preferred example, the material of the first active region metal layer 23 and the second active region metal layer 24 includes nickel, so the actual annealing temperature of the P-type active region is 800°C-900°C, and the actual annealing temperature of the N-type active region is 800-900°C. The actual annealing temperature of the source region is 1000°C-1200°C.

The forward conduction and reverse conduction performance of the SIC MOSFET device prepared according to the invention will be greatly improved.

In summary, the present invention provides a method for preparing a SIC MOSFET device, the preparation method comprising the steps of: providing a SIC substrate, forming a plurality of well regions of the first conductivity type arranged at intervals in the SIC substrate, located in the SIC substrate A first active region of the first conductivity type and a second active region of the second conductivity type in the well region, the second active region is adjacent to opposite sides of the first active region, and the first conductivity type is N type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type; a gate oxide layer and a gate conductive layer are formed on the substrate surface or in the substrate between the well regions, and a covering The gate dielectric layer of the gate conductive layer to obtain the gate structure; forming a first active area metal layer and a second active area metal layer, the first active area metal layer is located on the surface of the first active area and is in contact with the first active area The first active region is in contact, and the second active region metal layer is located on the surface of the second active region and is in contact with the second active region; for the first active region metal layer and the second active region metal layer Annealing is performed at different temperatures to respectively form the first ohmic contact and the second ohmic contact. In the process of preparing the SIC MOSFET device, the present invention adopts different annealing temperatures for the metal layer of the N-type region and the metal layer of the P-type region, so that the N-type and P-type regions are annealed at different optimum annealing temperatures, thereby making the P-type Both the ohmic contact region and the N-type ohmic contact region can obtain optimal contact resistivity, which is helpful to improve device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims

A kind of preparation method of SIC MOSFET device, it is characterized in that, described preparation method comprises steps:

A SIC substrate is provided, and a plurality of well regions of the first conductivity type arranged at intervals, a first active region of the first conductivity type and a second active region of the second conductivity type located in the well regions are formed in the SIC substrate. region, the second active region is adjacent to the opposite sides of the first active region, the first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type type;

forming a gate oxide layer and a gate conductive layer on the surface of the substrate between the well regions or in the substrate, and forming a gate dielectric layer covering the gate conductive layer to obtain a gate structure;

forming a first active area metal layer and a second active area metal layer, the first active area metal layer is located on the surface of the first active area and is in contact with the first active area, the second active area The region metal layer is located on the surface of the second active region and is in contact with the second active region;

Annealing is performed on the first metal layer in the active area and the metal layer in the second active area at different temperatures to form a first ohmic contact and a second ohmic contact respectively.
The preparation method according to claim 1, wherein a plurality of well regions of the first conductivity type arranged at intervals, and a first active region of the first conductivity type located in the well regions are formed in the SIC substrate. and the second active region of the second conductivity type include the steps of:

Forming a first mask layer on the SIC substrate, the pattern of the well region is defined on the first mask layer, and under the action of the first mask layer, the first conductivity type is carried out on the SIC substrate. ion implantation to form a plurality of well regions of the first conductivity type spaced apart in the SIC substrate;

Forming a second mask layer on the SIC substrate, the second mask layer defines the pattern of the second active region, under the action of the first mask layer and the second mask layer, the Ion implantation of the second conductivity type is performed in the well region, so as to form a plurality of the second active regions distributed at intervals in the well region;

A third mask layer is formed on the SIC substrate, the pattern of the first active region is defined on the third mask layer, and the first conduction is performed on the well region under the function of the third mask layer. type ion implantation to form the first active region in the well region;

Remove the remaining masking layer.
The preparation method according to claim 2, characterized in that, after removing the remaining mask layer, it further comprises the step of performing high-temperature annealing on the obtained structure to activate implanted ions and repair implanted damage.
The preparation method according to claim 3, characterized in that the high temperature annealing is carried out on furnace tube equipment, and the annealing temperature is greater than or equal to 800°C.
The preparation method according to claim 1, characterized in that, the preparation method further comprises the step of forming a plurality of lead-out electrodes and drain ohmic contacts after the ohmic contact is formed, and the plurality of lead-out electrodes are respectively connected to the first The active metal layer, the second active metal layer and the gate structure are electrically connected; the drain ohmic contact is located on the surface of the SIC substrate away from the gate structure.
The manufacturing method according to claim 1, characterized in that, the first metal layer in the active area and the second metal layer in the active area are connected and formed synchronously in the same process.
The preparation method according to claim 6, characterized in that, the material of the first metal layer in the active area and the metal layer in the second active area includes nickel.
The preparation method according to any one of claims 1-7, characterized in that annealing the first metal layer in the active region and the metal layer in the second active region is performed at different temperatures to form the first ohmic contact and the second metal layer respectively. The steps for the second ohmic contact include:

A protective layer is formed on the surface of the structure obtained after forming the first active area metal layer and the second active area metal layer, and the protective layer covers the P-type active area in the first active area and the second active area. district;

Simultaneous annealing is performed on the first active region and the second active region by laser annealing, wherein the actual annealing temperature of the P-type active region covered with the protective layer is lower than that of the first active region not covered with the protective layer and the actual annealing temperature of the N-type active region in the second active region.
The preparation method according to claim 8, wherein the actual annealing temperature of the P-type active region is 800°C-900°C, and the actual annealing temperature of the N-type active region is 1000°C-1200°C.
The preparation method according to claim 9, wherein the material of the first mask layer, the second mask layer and the third mask layer includes a silicon oxide layer and/or a polysilicon layer, and the protective layer includes Titanium nitride layer and/or silicon nitride layer.