RU2819581C1 - Method of making microwave ldmos-transistor crystals with multilayer drift drain region - Google Patents

Abstract

FIELD: microelectronic equipment.

SUBSTANCE: method of making microwave LDMOS-transistor crystals on a silicon substrate in a high-resistance p-type epitaxial layer includes forming source, drain, gate regions, several diffusion drain regions with different depth and degree of doping, and multilayer metallization using operations of photolithography, etching and ion doping of corresponding layers and regions. According to the invention, a drift drain region is formed, characterized by non-uniform and non-monotonic distribution of impurities in both longitudinal and transverse directions and consisting of four layers forming three sections, differing in depth and total depth of impurity atoms, in each of these sections, the local maximum of the impurity distribution is located at a certain depth.

EFFECT: invention makes it possible to produce microwave LDMOS-transistor crystals, which combine high reliability and improved values of specific electrical parameters, including drain current and drain-source resistance in open state.

1 cl, 8 dwg, 1 tbl

Description

Field of technology to which the invention relates:

The invention relates to the field of microelectronic technology and is used in the manufacture of high-power microwave LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors.

State of the Art:

There is a known method for manufacturing microwave LDMOS transistor crystals, patented by NXP and chosen as the first analogue [1], including the formation of a gate dielectric and polysilicon gate electrodes of elementary transistor structures on the surface of the epitaxial layer of original silicon substrates, creation in the epitaxial layer areas, lightly doped drift drain areas in the form of two series-connected stages of the same depth with a higher degree of alloying of the first stage (located closer to the gate) compared to the second, highly alloyed areas of drain and source of elementary transistor structures, as well as a two-layer field electrode (in [1] called shield structure) and a metallization system. Due to the formation of a two-layer drift drain area in the form of two series-connected stages and a two-layer field electrode, this manufacturing method makes it possible to create microwave LDMOS transistor crystals characterized by a high specific drain current and, as a consequence, a high specific output power.

The main disadvantage of the first analogue is the increase in the electric field strength near the gate due to the placement of a relatively highly doped drain drift region stage at its edge. This circumstance increases the injection of hot charge carriers into the dielectric layer near the gate during operation of the microwave transistor, which negatively affects the reliability of the device. Also, the high voltage of the electric field near the gate increases the risk of breakdown of the parasitic bipolar transistor, which leads to catastrophic failure of the device. Thus, the manufacturing method [1] makes it possible to improve the electrical parameters of microwave LDMOS transistors, but at the expense of their reliability.

Another well-known method for manufacturing microwave LDMOS transistor crystals, patented by JSC NPP Pulsar and chosen as a second analogue [2], involves the creation of end-to-end diffusion source areas of elementary transistor structures in the high-resistivity epitaxial p-layer of the original silicon substrates, growing a gate dielectric and forming silicon gate electrodes of elementary structures on the surface of a high-resistivity substrate layer, creating />regions of elementary transistor structures in high-resistance layer of the substrate by introducing boron ions into the substrate using polysilicon gate electrodes and photoresist layers as a protective mask and subsequent diffusion redistribution of the introduced impurity, the formation of multilayer drift drain regions (in [2] called multi-stage lightly doped drain areas) of elementary transistor structures, creation of highly doped drain and source areas of elementary transistor structures in the high-resistivity p-layer of the substrate through the introduction of arsenic ions into the substrate when using silicon gate electrodes and photoresist layers as a protective mask and subsequent diffusion redistribution of the embedded impurity, the formation of metal field electrodes, drain and gate electrodes of elementary transistor structures on the front side of the substrate and the common metal electrode of the source of the transistor structure on its back side. The key feature of this method is that the created multilayer (or according to the terminology [2] multistage) drift drain regions are characterized by a successively increasing depth and degree of doping of the stages in the direction from the polysilicon gate to the highly doped drainage areas. Thanks to this configuration of the drift drain regions, a significant reduction in the electric field strength near the gate and the injection of hot charge carriers is achieved.

The main disadvantage of the second analogue is a decrease in the specific drain current and an increase in the specific drain-source resistance in the open state. Thus, the manufacturing method [2] is characterized by high reliability of manufactured microwave LDMOS transistors, but does not allow achieving high specific electrical parameters.

A method for manufacturing microwave LDMOS transistor crystals, patented by Ampleon |3|, was chosen as a prototype. This method involves the formation of an epitaxial silicon layer substrates of polysilicon gate electrodes, ^-regions, lightly doped drift drain regions, highly doped areas of drain and source, field electrode (in |3] called electrically conductive shield element) and metallization system. The key feature of this method is the creation of a multilayer field electrode, including up to three layers. This configuration of the field electrode makes it possible to effectively suppress the electric field strength near the gate, and therefore the injection of hot charge carriers, and at the same time increase the impurity concentration in the drift regions of the drain in order to achieve high values of specific electrical parameters.

The main disadvantage of the prototype is the use of a simple, uniformly doped drift drain region. Because of this, despite the high values of specific electrical parameters compared to devices of previous generations, at present this design cannot provide the required level of parameters such as drain current and drain-source resistance in the open state, which largely determine the level of output power .

Disclosure of the invention:

The technical result of the present invention is the creation of a method for manufacturing a microwave LDMOS transistor crystal, which allows combining a low level of injection of hot charge carriers into the dielectric layer near the gate, minimal risk of breakdown of a parasitic bipolar transistor, outstanding values of specific electrical parameters, including drain current and drain-source resistance in open state, meeting modern requirements.

The technical result is achieved by the fact that in the known method of manufacturing a microwave LDMOS transistor crystal, including growing epitaxial layer (01) on silicon substrate (02) with crystallographic orientation (100), creating grooves in epitaxial layer 200-500 nm deep, creating deep source regions, creating drift drain regions (03), growing a sacrificial dielectric layer with a thickness of 300-600 A, forming gate steps by liquid etching of the sacrificial dielectric layer, growing a gate dielectric layer (04) with a thickness of 150-300 A, applying a layer to the gate dielectric layer polysilicon with a thickness of 200-500 nm, doping the polysilicon layer with phosphorus, forming elementary transistor structures from the polysilicon layer of gates (05) using plasma-chemical etching, creating -regions by the method of self-combined doping, application of a dielectric layer for the formation of spacers on the side faces of the gates, formation of spacers by the method of plasma-chemical etching, creation of highly alloyed areas of drain (06) and source, formation of drain, source and gate contacts of elementary transistor structures by creating cobalt silicide, deposition of a thick protective dielectric layer, formation of three-layer field electrodes (07) from a refractory electrically conductive material based on gitanium nitride, opening in a thick protective dielectric layer of contact windows, the formation of a metallization system consisting of five layers of aluminum-based metal, the formation of drift drain regions occurs from several layers (in several stages), due to which each drift drain region is characterized by a non-monotonic distribution of impurities in both longitudinal and transverse direction (Fig. 1-5). Moreover, the section of the drift regions of the drain closest to the gate (section 1 (08)) is characterized by the smallest depth and the average total depth of the number of impurity atoms, the section located in the middle of the drift region of the drain (section 2 (09)) is characterized by the average depth and the smallest total number of impurity atoms impurity atoms, the area located under region of the drain and near it (section 3 (10), is characterized by the greatest depth and the largest total number of impurity atoms in depth. In addition, in each of these sections of the drift regions of the drain, the local maximum of the impurity distribution is located not near the surface, but at some depth (Fig. 6). To create the listed sections, four layers of the drift area of the flow are used. To create section 3, the first (11) and second layers (12) of the drift area of the flow are used to create section 1. To create section 2, the second (12) and fourth (14) layers of the drift flow area are used, and to avoid the formation of a local maximum of impurity distribution at the border of sections 1 and 2, a gap of 0.1-0 is left between the third and fourth layers. .3 µm.

A comparative analysis with the prototype shows that the proposed method for manufacturing microwave LDMOS transistor crystals differs in the design and technological route for creating the drift drain region, a new set, execution sequence and modes of technological operations, as a result of which the drift drain region created before the formation of the polysilicon gate is characterized by uneven and non-monotonic impurity distribution in both longitudinal and transverse directions, and consists of four layers. A new fragment of the manufacturing process route includes the following technological operations: growing a sacrificial layer of silicon oxide, applying a layer of photoresist, opening windows in the photoresist layer using photolithography around the places where the drain areas (06), doping epitaxial layer (01) with phosphorus using the ion implantation method, followed by removal of the photoresist layer, carrying out diffusion distillation of the impurity to create the first layer of drift drain regions (11); applying a layer of photoresist, opening windows in the photoresist layer using photolithography, the boundaries of which correspond to the edges of the polysilicon gates (05) of two adjacent elementary transistor structures, doping epitaxial layer (01) with phosphorus using the ionic method, followed by removal of the photoresist layer to create a second layer of drift drain regions (12); applying a layer of photoresist, opening windows in the photoresist layer using photolithography, one boundary of which corresponds to the edges of polysilicon gates (05), and the second to the edges of field electrodes (07), doping epitaxial layer with phosphorus by ion implantation followed by removal of the photoresist layer - to create a third layer of drift drain regions (13); applying a layer of photoresist, opening windows in the photoresist layer using photolithography, the boundaries of which are 0.1-0.3 μm from the boundaries of the third layer of drift drain regions (13) of two adjacent elementary transistor structures, doping epitaxial layer (01) using the phosphorus ion implantation method, followed by removal of the photoresist layer and etching of the sacrificial layer of silicon oxide - to create a fourth layer of drift drain regions (14). Thus, the claimed method for manufacturing microwave LDMOS transistor crystals meets the “novelty” criterion of the invention.

In the inventive manufacturing method, the creation of section 1 (08) in the drift region of the drain with the smallest depth and average total depth of the number of impurity atoms relative to other sections makes it possible to increase the dosage of doping relative to the uniformly doped drift region of the drain (15) in the most important area from the point of view of carrier injection processes charge from the channel and current spreading in the drift region, thereby achieving a high value of the specific drain current and a low value of the specific drain-source resistance in the open state of the microwave LDMOS transistor (Table 1).

In the inventive method for manufacturing crystals, the creation in the drift region of the drain of section 2 (09) with an average depth and the smallest total number of impurity atoms relative to other sections of the drift region makes it possible to compensate for the increase in the dosage of doping in section 1 and to ensure the same level of drain-source breakdown voltage, the same as the uniformly doped drift drain region (15). The large depth of this section makes it possible to compensate for the increase in resistance caused by the relatively small total number of impurity atoms over the depth.

In the inventive manufacturing method, the creation of section 3 (10) in the drift region of the drain with the greatest depth and the largest total number of impurity atoms relative to other sections makes it possible to achieve breakdown of LDMOS structures by drain-source voltage in the vertical direction, thereby minimizing the risk of breakdown of parasitic bipolar transistor.

Achieving in the inventive method of manufacturing a maximum impurity concentration along the depth of the drift region of the drain not near the surface, but at a certain depth, makes it possible to reduce the current density near the surface of the structure (Fig. 7, 8), where the electric field strength is especially high, thereby compensating for the increase in electric field strength in section 1, caused by an increase in the dosage, and reduce the level of injection of hot charge carriers.

Taken together, these factors make it possible to simultaneously achieve a low level of injection of hot charge carriers, a minimal risk of breakdown of a parasitic bipolar transistor, a high specific drain current and a low specific drain-source resistance in the open state. In this way, an improvement in the electrical parameters and reliability of the microwave transistor is achieved, that is, it exhibits a new technical property. Consequently, the proposed method for manufacturing microwave LDMOS transistor crystals meets the “inventive step” criterion.

Description of drawings:

In fig. Figure 1 shows a diagram of a multilayer drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals, on which sections 1, 2 and 3 are indicated. This image is of a schematic nature, the relative sizes of the elements depicted on it do not correspond to the elements of a real transistor crystal .

In fig. 2 shows the stage of creating the first layer of the drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals - step 2 of the description of the method for implementing the invention. This image is of a schematic nature; the relative sizes of the elements depicted on it do not correspond to the elements of a real transistor crystal.

In fig. Figure 3 shows the stage of creating the second layer of the drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals - step 3 of the description of the method for implementing the invention. This image is of a schematic nature; the relative sizes of the elements depicted on it do not correspond to the elements of a real transistor crystal.

In fig. 4 shows the stage of creating the third layer of the drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals - step 4 of the description of the method for implementing the invention. This image is of a schematic nature; the relative sizes of the elements depicted on it do not correspond to the elements of a real transistor crystal.

In fig. Figure 5 shows the stage of creating the fourth layer of the drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals - step 5 of the description of the method for implementing the invention. The gap between the third and fourth layers is increased for clarity, also in Fig. 5 does not take into account the influence of diffusion distillation of impurities carried out at step 6 of the description of the method for implementing the invention. This image is of a schematic nature; the relative sizes of the elements depicted on it do not correspond to the elements of a real transistor crystal.

In fig. Figure 6 shows the distribution of phosphorus concentration in depth in sections 1 (16), 2 (17) and 3 (18) of the model of a multilayer drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals, and the model of a uniformly doped drift drain region - those. as in the prototype (19). The distribution of phosphorus concentration in the model of a uniformly doped drift drain region corresponds to the condition for achieving the maximum level of drain-source breakdown voltage.

Figure 7 shows the current density distribution in the model of a multilayer drift drain region created in accordance with the proposed method for manufacturing microwave LDMOS transistor crystals. The main electrical parameters of this model are given in Table 1 in the column “Multilayer DOS”.

In fig. Figure 8 shows the current density distribution in the model of a uniformly doped drift drain region (as in the prototype). The main electrical parameters of this model are given in Table 1 in the “Uniform DOS” column.

The following notations are introduced in the listed figures:

01 - epitaxial layer;

02 - silicon substrate;

03 - drift drainage area;

04 - gate dielectric layer;

05 - shutter;

06 - drainage area;

07 - field electrode;

08 - section 1 of the drift drain area, located at the edge of the gate;

09 - section 2 of the drift flow area, located in its middle;

10 - section 3 of the drift drainage area, located under the drainage area and its vicinity;

11 - first layer of the drift drainage area;

12 - second layer of the drift area of the drain;

13 - third layer of the drift drainage area;

14 - fourth layer of the drift drainage area;

15 - uniformly doped drift drain region;

16 - distribution of phosphorus concentration by depth in section 1 of the model of a multilayer drift region of runoff;

17 - distribution of phosphorus concentration in depth in section 2 of the model of a multilayer drift region of runoff;

18 - distribution of phosphorus concentration in depth in section 3 of the model of a multilayer drift runoff area;

19 - distribution of phosphorus concentration along the depth of the model of a uniformly doped drift region of the drain (as in the prototype);

20 - electrical contact to drainage areas. Implementation of the invention:

The invention is carried out as follows.

1. A semiconductor structure is created using a known method for manufacturing microwave LDMOS transistor crystals, including growing epitaxial layer (01) on silicon substrate (02) with crystallographic orientation (100), creating a groove in epitaxial layer with a depth of 200-500 nm, creating a deep source region and filling the groove with a dielectric layer.

2. By growing a sacrificial layer of silicon oxide 100-300 A thick, applying a layer of photoresist, opening windows in the photoresist layer using photolithography around the places where the drain areas (will be created in step 6) (06), by doping epitaxial layer (01) with phosphorus by the method of ion implantation with an ion energy of 200-300 keV and a dose of 0.06-0.16 μC/cm, followed by removal of the photoresist layer, diffusion distillation of the impurity at a temperature of 1000°C for 50-100 minutes is created the first layer of drift drainage areas (11) - Fig. 2.

3. By applying a layer of photoresist, opening windows in the photoresist layer using photolithography, the boundaries of which correspond to the edges of the polysilicon gates (05) of two adjacent elementary transistor structures (which will be created in step 6), doping epitaxial layer (01) with phosphorus using the method of ion implantation with an ion energy of 60-90 keV and a dose of 0.05-0.1 μC/cm ² , followed by removal of the photoresist layer, a second layer of drift drain regions (12) is created - FIG. 3.

4. By applying a layer of photoresist, opening windows in the photoresist layer using photolithography, one boundary of which corresponds to the edges of the polysilicon gates (05), and the second to the edges of the field electrodes (which will be created in step 7) (07), doping epitaxial layer (01) with phosphorus by the method of ion implantation with an ion energy of 150-250 keV and a dose of 0.3-0.5 μC/cm ² , followed by removal of the photoresist layer, a third layer of drift drain regions is created (13) - Fig. 4.

5. Applying a layer of photoresist, opening windows in the photoresist layer using photolithography, the boundaries of which are spaced from the boundaries of the third layer of drift drain regions (13) of two adjacent elementary transistor structures by 0.1-0.3 μm, doping the p-epitaxial layer (01) phosphorus by the method of ion implantation with an ion energy of 200-300 keV and a dose of 0.24-0.4 μC/cm ² , followed by removal of the photoresist layer and etching of the sacrificial layer of silicon oxide, a fourth layer of drift drain regions is created (14) - Fig. 5.

6. In accordance with the known method of manufacturing microwave LDMOS transistor crystals, a sacrificial layer of silicon oxide with a thickness of 300-600 A is grown, a gate step is formed by liquid etching of the sacrificial layer, a gate dielectric layer is grown with a thickness of 150-300 A, and a layer is applied to the gate dielectric layer. polysilicon with a thickness of 200-500 nm, doping the silicon layer with phosphorus, forming elementary transistor structures from the polysilicon layer of gates (05) using plasma-chemical etching, creating areas using the method of self-combined doping, carrying out diffusion distillation of impurities at a temperature of 1000°C for 50-100 minutes, applying a dielectric layer to form spacers on the side faces of the gates, forming spacers using plasma-chemical etching, creating highly alloyed drain (06) and source areas, formation of drain, source and gate contacts of elementary transistor structures by creating cobalt silicide, deposition of a thick protective dielectric layer.

7. By depositing a layer of refractory electrically conductive material based on titanium nitride, applying a layer of photoresist, forming the required topological pattern in the photoresist layer using photolithography, and plasma-chemical etching of a conductor layer based on titanium nitride using the resulting photoresistive mask, a field electrode (07) is formed above the drift drain area.

8. By deposition of a dielectric layer, chemical-mechanical polishing of the deposited layer, deposition of a photoresist layer, formation of the required topological pattern in the photoresist layer by photolithography, plasma-chemical etching of the resulting photoresist mask of the dielectric layer, filling of etched contact windows with tungsten, chemical-mechanical polishing of the tungsten layer, electrical contacts to the n ⁺ -regions of drain (20), source and gate.

9. By applying a layer of conductive material based on aluminum, applying a layer of photoresist, forming the required topological pattern in the photoresist layer using photolithography, and plasma-chemical etching using the resulting photoresist mask of the conductive layer, a layer of the first metal is created.

10. By deposition of a dielectric layer, chemical-mechanical polishing of the deposited layer, deposition of a photoresist layer, formation of the required topological pattern in the photoresist layer by photolithography, plasma-chemical etching of the resulting photoresist mask of the dielectric layer, dusting of etched contact windows with tungsten, chemical-mechanical polishing of the tungsten layer, the first interlayer contact holes.

11. By analogy with steps 9 and 10, the following are sequentially created: the second layer of metal, the second interlayer contact holes, the second layer of metal, the second interlayer contact holes, the third layer of metal, the third interlayer contact holes, the fourth layer of metal, the fourth interlayer contact holes, the fifth layer metal

12. By depositing a passivating dielectric layer, applying a photoresist layer, forming the required topological pattern in the photoresist layer using photolithography, and plasma-chemical etching of the passivating dielectric layer over the resulting photoresist mask, contact pads of the transistor crystal are created.

Information sources:

1. US patent US 7521768 (132) “Electric device comprising an LDMOS transistor”, published 04/21/2009 (analogue).

2. RF patent RU 2498448 (C1) “Method for manufacturing microwave LDMOS transistors”, published on November 10, 2013 (analogue).

3. European patent EP 2383786 (B1) ((Semiconductor transistor comprising two electrically conductive shield elements", published 08/15/2018 (prototype).

Claims (1)

A method for manufacturing microwave LDMOS transistor crystals, including growing a p ^- -epitaxial layer on a silicon p ⁺ -substrate with crystallographic orientation (100), creating grooves in the p ^- -epitaxial layer, creating deep p ⁺ -source regions, creating drift drain regions, growing a sacrificial dielectric layer, forming gate steps by liquid etching of a sacrificial dielectric layer, growing a gate dielectric layer, applying a polysilicon layer to a gate dielectric layer, doping a polysilicon layer with phosphorus, forming elementary transistor structures from a polysilicon layer using plasma-chemical etching, creating p ^- -regions by the method of self-combined doping, application of a dielectric layer to form spacers on the side faces of the gates, formation of spacers by plasma-chemical etching, creation of highly doped n ⁺ -drain and source regions, formation of drain, source and gate contacts of elementary transistor structures by creating cobalt silicide, deposition of a thick protective dielectric layer, formation of three-layer field electrodes from a refractory electrically conductive material based on titanium nitride, opening of contact windows in a thick protective dielectric layer, formation of a metallization system consisting of five layers of aluminum-based metal, characterized in that the formation of drift drain areas occurs from several layers , forming three sections, and the section closest to the gate is characterized by the smallest depth and the average total depth of the number of impurity atoms, the section located in the middle is characterized by the average depth and the smallest total depth of the number of impurity atoms, the section located under the n ⁺ -drain region and near it, is characterized by the greatest depth and the largest total depth of impurity atoms; in addition, in each of these areas, the local maximum of the impurity distribution is located not near the surface, but at a certain depth.