RU2498448C1 - Manufacturing method of shf ldmos transistors - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: in method of SHF LDMOS transistors manufacturing, including manufacturing of feed-through diffusive source p⁺-junctions of elementary transistor cells in high-ohmic epitaxial p^--layer of the source p^-p⁺-silicone substrate, growing of gate dielectric and formation of polysilicone electrodes for gate of elementary cells at the surface of high-ohmic p^--layer of the substrate, creation of p-wells for elementary cells in high-ohmic p--layer of the substrate by means of boron ion introduction into the substrate using polysilicone electrodes for the gate and photoresist coatings as a mask and subsequent diffusive redistribution of the introduced additive; when p-wells are made gate dielectric between polysilicone electrodes for the gate of elementary cells is reduced to thickness of 100-300 Ǻ, to the substrate face the first protective photoresist coating is applied, two gaps in the first protective photoresist coating are opened simultaneously respectively at the place of heavy-alloyed n⁺-regions of drain and source of the elementary cells and phosphorus ions are introduced through them with dose of 0.2-0.6 mcC/cm and energy of 80-140 keV and arsenic ions with dose of 400-500 mcC/cm and energy of 40-80 keV; then the second drain gap is opened and phosphorus ions are introduced through it in the same dose and energy as to the first drain; then the third drain gap is opened and phosphorus ions are introduced through it with less dose and energy in comparison with the second drain; then next grades of lightly-alloyed n^--drain regions of elementary cells are formed in similar way. Phosphorus ions are implanted to the next grade with a less dose and energy in comparison with the previous one; thereafter remainders of protective photoresist layer are removed from the substrate face and simultaneous up-diffusion of the introduced additives of phosphorus and arsenic is made.

EFFECT: creating method for manufacturing of powerful silicone SHF LDMOS transistors with reduced transistor cell spacing, improved frequency and energy parameters and higher percent of fit structures output.

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Description

The invention relates to electronic semiconductor technology, in particular to methods for manufacturing high-power silicon microwave microwave LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors and can be used to create a new generation of electronic equipment on their basis.

A known method of manufacturing LDMOS transistor structures (US Patent No. 6020611 "Semiconductor component and method of manufacture", published 1.02.2000), selected as the first analogue, including growing a gate dielectric and forming polysilicon gate electrodes of elementary transistor cells on the surface high-resistance epitaxial p ^- layer of the initial silicon p ^- p ⁺ substrate, creation of p-pockets in the high-resistance p ^- layer, lightly doped n ^- regions of the drain in the form of two series-connected n ^- steps of the same depth with a higher degree of doping of the second stage compared with the first, as well as highly doped n ⁺ regions of the drain and the source of unit cells by introducing boron and arsenic ions into the substrate, respectively, using polysilicon gate electrodes and photoresist layers as a protective mask and subsequent diffusion redistribution of the embedded impurity in each of the above components of the transistor structure.

The main disadvantage of this analogue is the extremely inhomogeneous distribution of the electric field in the transistor LDMOS structure with a significantly increased magnitude of its intensity (up to 4.0 ... 4.2 V / cm) at the edges of n ^- steps directly adjacent to the highly doped n ^{+ region of the} drain and p-pocket of unit cells, which leads to a sharp decrease in the breakdown voltage of the drain pn junction (≤60 V) and increased injection of hot carriers into traps in the gate dielectric with all the negative consequences that follow from this (see Strongly «Hot hole degradation effects in lateral nDMOS transistors» - IEEE Transactions on Electron Devices, October 2004, vol.51, N10, p.1704-1710).

In another known method for manufacturing microwave LDMOS transistors, selected as the second analogue (US Patent No. US6686627B2 "Multiple conductive plug structure for lateral RF MOS devices", published February 3, 2004), a more uniform distribution of the electric field in the transistor structure is achieved by forming lightly doped n ^- regions of the drain of elementary cells from 4 steps, moreover, not identical in depth, but with successively increasing depth and degree of doping in the direction from the polysilicon gate electrode to the high doped n ⁺ region flow, using phosphorus ions instead of arsenic as a dopant and placing highly doped n ⁺ regions of the runoff of unit cells within the volume of the last lightly doped n ^- rung of the runoff. However, the main aspect of the second analogue method, aimed at organizing the relationship between the source electrodes of the unit cells with the common source electrode of the transistor structure through the through grooves etched in the high-resistance epitaxial p ^- layer of the substrate, seems very problematic from the point of view of cost-effective industrial production, which can attributed to a serious drawback of this analogue.

As a prototype, a method for manufacturing LDMOS transistors was selected (US Patent No. 7315062 B2 “Semiconductor device, mask for impurity implantation, and method of fabricating the semiconductor device”, published January 1, 2008), including: the creation of through diffusion source p ⁺ jumpers unit cells in the high-resistance p ⁺ -layer of the initial silicon p ^- p ⁺ -substrate (instead of through grooves in the 2nd analogue method); growing a gate dielectric and forming polysilicon electrodes of a gate of elementary cells on the surface of a high-resistance p ^- layer of a substrate; creation of p-pockets in the high-resistance p ^- layer, multistage lightly doped n ^- drain regions with a smooth gradient of dopant change between n ^- steps and highly doped n ⁺ drain regions and the unit cell source by introducing boron and phosphorus ions into the substrate, respectively and arsenic when using a shutter polysilicon electrode and photoresist layers as a protective mask and the subsequent diffusion redistribution of the embedded impurity in each of the above transistor elements noy structure; the formation of additional grounded metal shielding electrodes on the surface of the interlayer dielectric in the gap between the drain electrodes and the gate of the unit cells. Such an approach to the fabrication of a transistor LDMOS structure in the prototype method provides a fairly uniform distribution of the electric field with a reduced value of its intensity in lightly doped n ^- regions of the drain of unit cells to 2.0 to 2.8 V / cm and thus allows the breakdown voltage of stock pn junction at the level of 70 ... 75 V and minimize the probability of injection of hot carriers into the gate insulator. However, in this case, this is achieved due to a serious complication of the topological pattern of the used photomasks, an increase in the length and number of steps in the lightly doped n ^- regions of the drain of elementary cells, which naturally leads to an increase in the step of the transistor cell, a decrease in the frequency and energy parameters of the device, an increase in labor input, and a decrease percent yield of crystals on the plate. The decrease in the percentage of yield of suitable crystals in the prototype method also contributes to the fact that in it phosphorus and arsenic ions are embedded directly into the silicon substrate, not coated with a thin layer of dielectric.

The technical result of the present invention is the creation of a method of manufacturing high-power silicon microwave LDMOS transistors with a reduced step of the transistor cell, improved frequency and energy parameters, with reduced labor intensity and increased percentage of yield of crystals on the wafer.

The technical result is achieved by the fact that in the known method of manufacturing microwave LDMOS transistors, including the creation of through diffusion source p ⁺ jumper of elementary transistor cells in a high resistance epitaxial p ^- layer of the original silicon p ^- p ⁺ substrate, growing a gate dielectric and forming polysilicon electrodes unit cells on the surface of the high-resistance p ^- layer of the substrate, the creation of p-pockets of unit cells in the high-resistance p ^- layer of the substrate by incorporating boron ions into the substrate using a polysilicon gate electrode and photoresist layers as a protective mask and subsequent diffusion redistribution of the embedded impurity, the formation of multistage lightly doped n ^- regions of the drain of unit cells with a successively increasing depth and degree of doping of steps in the direction from the polysilicon gate electrode to the high doped n ^{+ region of the} drain by introducing phosphorous ions into the high-resistance p ^- -layer substrate when used as a protective mask polysilicon evyh gate electrodes and the resist layers and subsequent diffusion of the implanted impurity redistribution in each stage, the creation of high n ⁺ source and drain-regions of elementary cells in the high-resistance p ^- -layer substrate by introducing arsenic ions into the substrate when used as a protective mask and the polysilicon gate electrodes layers of the photoresist and subsequent diffusion redistribution of the embedded impurity, the formation of metal screens, drain electrodes and the gate of unit cells onto on the back side of the substrate and the common metal electrode, the source of the transistor structure on its back side, after creating p-pockets, the gate dielectric between the polysilicon gate element electrodes is thinned to a thickness of 100 ... 300 Å, the first protective layer of the photoresist is applied to the front side of the substrate, they are opened simultaneously by photolithography two windows in the first protective layer of the photoresist, respectively, at the location of the high-doped n ⁺ -regions of the drain and the source of unit cells, and are inserted through them into the base phosphorus ions with a dose of 0.2 ... 0.6 µC / cm ² and an energy of 80 ... 140 KeV and arsenic ions with a dose of 400 ... 500 µC / cm ² and an energy of 40 ... 80 keV, then the second stock window in the second is opened by photolithography a protective layer of photoresist, bordering the periphery of the first stock window and through the second stock window, phosphorus ions are implanted into the substrate with the same dose and energy as in the first stock window, then the third stock window in the third protective layer of photoresist bordering the periphery is opened by photolithography second stock window and through the third hundred ovoe window is embedded in the substrate with phosphorus ions at an energy and dose than the second stock window, then similarly formed subsequent stage lightly doped n ^- -regions Photo elementary cells, and in each following stage of phosphorus ions are implanted at a dose and energy as compared with of the previous one, after that the residues of the photoresist protective layer are removed from the front side of the substrate and simultaneous diffusion acceleration of phosphorus and arsenic impurities embedded in the substrate is carried out.

Comparative analysis with the prototype shows that the inventive method is distinguished by the presence of a new set and sequence of technological operations: the creation of multi-stage lightly doped runoff n ^- regions after the formation of high-alloyed n ⁺ regions of runoff and the source of unit cells, and not in the reverse order; the formation in the high-resistance epitaxial p ^- layer of the substrate of multistage lightly doped runoff n ^- regions with successively decreasing depth and degree of step doping in the direction from the high doped n ^{+ region of the} drain to the polysilicon gate electrode of the unit cells; initial opening of windows in the protective layer of the photoresist in the area of dislocation of highly doped n ⁺ regions of the drain and the source of unit cells and the successive introduction of phosphorus and arsenic ions through them into the substrate with a certain dose and energy; the formation of the second stage of lightly doped n ^- regions of runoff of unit cells around highly doped n ^{+ -} regions of runoff by introducing phosphorus ions into the second stock window with the same energy and dose as in the first stock window; simultaneous diffusion distillation of phosphorus and arsenic impurities embedded in the substrate during the formation of multistage lightly doped runoff n ^- regions and highly doped n ⁺ regions of runoff and the source of unit cells; thinning the gate dielectric between the polysilicon electrodes of the gate of the unit cells to a certain thickness at a certain stage of manufacturing a transistor structure. Thus, the claimed method meets the criteria of the invention of "novelty."

Autopsy in the inventive method in the first protective layer of the photoresist of the first stock window simultaneously with the source and the introduction through them into the substrate of phosphorus and arsenic ions with the doses and energies specified by the claims, allows:

- to form highly doped n ⁺ regions of runoff and source to create lightly doped n ^- regions of runoff of unit cells;

- place highly doped n ⁺ -regions of the drain inside the volume of the deepest first stage of lightly doped n ^- -regions of the drain of unit cells and thus realize the breakdown voltage of the pn junction for the specific transistor structure;

- completely eliminate the tolerance on the error of combining highly doped n ⁺ -regions of the drain with the first stage of lightly doped n ^- -regions of the drain of elementary cells and thereby reduce the step of the transistor cell, and therefore improve the frequency and energy parameters of the device and increase the number of crystals on the plate.

Opening the second stock window in the second protective layer of the photoresist, bordering the periphery of the first stock window and introducing phosphorus ions through it into the substrate with the same energy and dose as in the first stock window, allows using a simpler topological design a set of photomasks, compared with the prior art, to provide a more gradual change in gradient at the ends of the dopant lightly doped n ^- -regions Photo immediately adjacent to a high-alloy n ⁺ -region Elementary cell current and thus increase the breakdown voltage stock pn junction, but due to use of cheaper set of photomasks to reduce the cost and complexity of manufacturing crystals.

The formation in the present method of lightly doped n ^- -regions of runoff of unit cells by introducing phosphorus ions into each subsequent step with a lower dose and energy compared to the previous one provides a complete and more uniform distribution of the dopant in each step compared to the prototype and analogues, and allows such a way to increase the electrical conductivity of lightly doped n ^- regions of the drain of unit cells, and hence the power capabilities of the device.

Carrying out in the present method a simultaneous diffusion distillation of impurities of phosphorus and arsenic embedded in the substrate, instead of multiple separate in the prototype and analogues, allows to reduce the number and total duration of high-temperature technological operations and, as a result, reduce the depth of lightly doped n ^- regions of the runoff of unit cells, optimize the high resistance thick epitaxial p ^- -layer initial silicon p ^- p ⁺ -podlozhki, reduce labor intensity and increase the percent recovery crystals on plate-period.

The thinning in the inventive method of the gate dielectric between the polysilicon electrodes of the gate of the unit cells to a thickness of 100 ... 300 Å after the creation of p-pockets allows you to:

- to provide free penetration through a thinner oxide compared to the gate dielectric in the substrate of low-energy phosphorus and arsenic ions (20 ... 30 keV);

- eliminate or significantly weaken the channeling effect of phosphorus and arsenic ions embedded in the substrate and thus realize a more uniform distribution front of the dopant in the high-resistance p ^- layer of the substrate without the appearance of a second maximum at a greater depth;

- reduce the number of structural defects in the high-resistance epitaxial p ^- layer of the substrate upon incorporation of phosphorus and arsenic ions with a high dose and energy into it and thus increase the electrical conductivity of the formed near-surface regions of the drain and the source of transistor unit cells;

- to grow, in each case, the optimum thickness of the gate insulator.

In the present invention, the new combination and the sequence of technological operations allows, in contrast to the prototype method, to reduce the step of the transistor cell and, all other things being equal, create powerful silicon LDMOS microwave transistors with breakdown voltage of the drain pn junction U _c . _Probe = 75 ... 90 V, operating frequency range up to 3.0 ... 3.5 GHz at supply voltage U drain _c.pit = 32 ... 40 V with improved frequency and energy parameters, that is, it exhibits a new technical property. Therefore, the claimed method meets the criterion of "inventive step".

In figures 1 ... 7 shows the main stages of the manufacture of microwave LDMOS transistor structures according to the claimed method.

Example.

Based on the proposed method, samples of silicon n-channel LDMOS structures (crystals) of 4.2 mm × 1.0 mm in size with a five-step lightly doped n ^- region of the drain of unit cells 3.2 microns in length were prepared (the main parameters of the technological process for their formation are presented in table 1), the length and total width of the induced n-channel of unit cells, respectively, L _k = 0.6 μm and W _k = 78 mm, designed to operate in the frequency range up to 3.0 ... 3.5 GHz with a drain voltage of U _s.pit = 32 ... 40 V. The starting material for Silicon p ^- p ⁺⁺ substrates (1), oriented along the (100) plane, with an upper high-resistance epitaxial p ^- layer with a thickness h _p- = 7.0 ... 7.5 μm and resistivity ρ _p- served as the transistor structures. = 10 ... 12 Ohm · cm and the lower highly doped p ⁺⁺ layer with ρ _{p ++} = 0.005 Ohm · cm.

The method is as follows:

1. The incorporation of boron ions into a substrate with an energy of 80 keV and a dose of 500 μC / cm ² and subsequent diffusion redistribution of the embedded impurity at a temperature T = 1100 ° C in a nitrogen medium forms through source p ⁺ jumper wires (2) of unit cells in a high-resistance p ^- -layer of the substrate (1) - figure 1.

2. By the pyrogenic oxidation of silicon at T = 850 ° C, a gate insulator (3) with a thickness of 800 Å is grown on the surface of a high-resistance epitaxial p ^- layer of the substrate, the gate insulator is coated with a 0.5-μm phosphorus-doped polysilicon layer, formed from a polysilicon layer by the method photolithography, rectangular longitudinal teeth (4) of unit cells 0.7 ... 0.75 μm wide and 340 μm long with a distance between adjacent gate teeth L _window = 6.4 μm, create p-pockets (5) of transistor cells by introducing ions into the substrate bo with an energy of 40 keV and a dose of 3.0 ... 5.0 μC / cm ² when using shutter electrodes (4) and photoresist layers as a protective mask and subsequent diffusion redistribution of boron impurity embedded in the substrate at T = 1000 ° C in nitrogen - figure 1, table 1.

3. The gate dielectric between the polysilicon electrodes of the gate (4) of the transistor unit cells is thinned to a thickness of 100 ... 300 Å, the first protective layer of positive photoresist (6 ₁ ) 0.4 ... 0.45 μm thick is applied to the front side of the substrate (1), and opened in the protective a photoresist layer (6 ₁₎ by photolithography window (7), _{the window} width of L = 2.0 m, and (8), respectively, in place of high-dislocation-type regions n ⁺ drain and source terminals of the unit cells and introducing therethrough a high-resistance p ^- -layer substrate ions phosphorus (9) with an energy of 100 keV and a dose of 0.2 SCLC / cm ² and yshyaka (10) and (10 ₁₎ with an energy of 80 keV and a dose of 500 SCLC / cm ² - 1, Table 1.

4. The method of photolithography is opened in the second protective layer of photoresist (6 ₂₎ second stock box (11) _{the window} width L = 3.4 m, bordering circumferentially stock first window (7) in the region of 0.7 microns, and introducing through the windows ( 11) phosphorus ions (12) with the same dose of 0.2 μC / cm ² and an energy of 100 keV as in the 1-stock window (7) - figure 2, table 1, into the substrate.

5. The method of photolithography autopsied at the third protective photoresist layer (6 ₃₎ third stock box (13) _{the window} width L = 4.6 m, peripherally bordering second stock box (11) in the region of 0.6 microns, and introducing through the windows ( 13) phosphorus ions (14) with an energy of 80 keV and a dose of 0.15 μC / cm ² into the substrate - Fig. 3, table 1.

6. Using the photolithography method, a fourth stock window (15) with a width L _con = 5.6 μm, bordering the third stock window (13) at a distance of 0.5 μm bordering the periphery, is opened in the fourth protective layer of the photoresist (6 ₄ ) and inserted through the windows ( 15) phosphorus ions (16) with an energy of 60 keV and a dose of 0.1 μC / cm ² into the substrate - Fig. 4, table 1.

7. Using the photolithography method, the fifth stock window (17) with a width of L _con = 6.4 μm, bordering the fourth stock window (15) at a distance of 0.4 μm at the periphery, is opened in the fifth protective layer of the photoresist (6 ₅ ) and inserted through the windows ( 17) phosphorus ions (18) with an energy of 40 keV and a dose of 0.05 μC / cm ² into the substrate - Fig. 5, table 1.

и конечные глубины

каждой из пяти ступеней после диффузионной (d_диф) разгонки примеси фосфора соответственно при температуре Т=900°C в течении 30 минут и при Т=1000°C в течении 20 минут.8. The residues of the protective layer of the photoresist (65) are removed from the front surface of the substrate, simultaneous diffusion acceleration of impurities of phosphorus and arsenic introduced into the substrate is carried out at the temperature necessary for their maximum activation, and as a result, highly alloyed in the high-resistance epitaxial p ^- layer of the substrate (1) n ⁺ regions of runoff (10 ₁ ) and source (10 ₂ ) and, respectively, the first (9 ₁ ), second (12 ₁ ), third (14 ₁ ), fourth (16 ₁ ) and fifth (18 ₁ ) steps of lightly doped n ^- -regions of runoff of unit cells - Fig.6, 7. Table 1 presents the total accumulated doses of phosphorus ions □ D, maximum impurity concentrations N _max , average projected ranges of phosphorus ions

and final depths

each of the five steps after diffusion (d _differential ) distillation of phosphorus impurities, respectively, at a temperature of T = 900 ° C for 30 minutes and at T = 1000 ° C for 20 minutes.

9. An interlayer dielectric (19) is formed from a layer of borophosphorosilicate glass previously deposited on the front side of the substrate, in which contact windows are opened by photolithography over the polysilicon gate electrodes (4), highly doped n ⁺ regions of the drain (10 ₁ ) and source (10 ₂ ) unit cells, a layer of aluminum with copper and silicon additives 2.5 ... 3.0 μm thick is applied to the interlayer dielectric and photolithography method creates metal source electrodes (20), drain (21), shunt metal polysilicon layers gate electrodes (22) and metal shielding electrodes (23) connected to the source electrodes (20) of the unit cells (connecting conductors are not shown in Figure 6). A common metal electrode of the source of the transistor structure (24) on the back side of the substrate was created when the crystal was soldered to the heat sink surface of the case using a gold gasket, and the induced n-channel (25) was formed at the ends of p-pockets (5) adjacent to the gate insulator (3 ) when a positive voltage is applied to the gate electrode of the transistor structure - 6, 7.

The yield of crystals on the plate made by the present method was about 49%. Suitable crystals mounted in a modified KT-25 metal-ceramic case without beryllium ceramics had a breakdown voltage of the drain pn junction U _s.probe = 80 ... 85 V and with a supply voltage across the drain U _s.pit = 40 V in class AB mode, the pulse duration τ _p = 300 μs, duty cycle Q = 10, at a frequency of 3.1 GHz, the power P _out = 38 ... 40 W was given to the load with a power gain K _ur = 10 ... 12 dB and a drain coefficient η _c = 42 ... 45%.

Similarly prepared samples of LDMOS transistor structures, in which arsenic ions with a dose exceeding 500 μC / cm ² were introduced into the substrate through the first drainage window in the protective layer of the photoresist, had exactly the same parameters, however, there were undesirable problems associated with the subsequent removal of the protective layer of photoresist from the front surface of the substrate.

Comparing the above parameters with similar parameters of the prototype and well-known foreign silicon microwave LDMOS transistors, designed for the operating frequency range up to 3.0 ... 3.5 GHz, we can draw the following conclusions:

1. The inventive method allows to realize the breakdown voltage identical to the prototype pn junction of the created LDMOS structures at a significantly smaller (by 15 ... 30%) step of the unit transistor cell, using a simpler configuration of the topological pattern of the set of photo templates, with a reduced number and a reduced total duration performed high-temperature technological operations and, as a result, improve the frequency and energy parameters of the device, increase the number of crystal in on the plate, reduce the complexity and cost of manufacturing crystals, increase the percentage of yield of suitable crystals.

2. The inventive method allows you to create powerful silicon microwave LDMOS transistors that are comparable with modern foreign counterparts in the main electrical parameters, but are able to work in comparison with them at higher supply voltages along the drain (U _{s.pit ≤40} V instead of U _s.pit = 32 V for transistors BLS2933-100 from Philips, BLS6G3135-120, BLS7G2729-350P from NXP, MRF7S35120HSR3, MRF8P29300HR6 from Freescale Semiconductor and others).

The technical and economic efficiency of the proposed method consists in the possibility of manufacturing high-power silicon microwave LDMOS transistors with improved frequency and energy parameters, the organization of their cost-effective industrial production and the creation of new generation electronic equipment with higher technical and economic characteristics based on these devices.

Information sources:

1. US patent No. 6020611 "Semiconductor component and method of manufacture", published 1.02.2000, (analog).

2. US patent No.US 6686627 B2 "Multiple conductive plug structure for lateral RF MOS devices", published February 3, 2004 (analogue).

3. US patent No. US 7315062 B2 "Semiconductor device, mask for impurity implantation, and method of fabricating the semiconductor device", published January 1, 2008 (prototype).

Claims (1)

A method of manufacturing microwave LDMOS transistor comprising forming through-diffusion of source p ⁺ -peremychek elementary transistor cells in the high-resistivity epitaxial p ^- -layer initial silicon p ⁺ p ^- -podlozhki, growing gate dielectric and forming polysilicon gate electrodes of the unit cells on the surface of a high-resistance p ^{- -} substrate layer, creating p-pockets elementary cells in high-resistance p ^- -layer substrate by introducing boron ions into the substrate using as a mask the polysilicon protective x gate electrodes and the resist layers and subsequent diffusion of the implanted impurity redistribution, multistage forming lightly doped n ^- -regions Photo unit cells sequentially with increasing depth and the degree of doping levels in a direction from the polysilicon gate electrode to the n ⁺ -region high-flow by introducing phosphorous ions into the high impedance p ^- -layer substrate when used as a protective mask and the polysilicon gate electrode layers of photoresist and subsequent diffusion of the implanted impurity redistribution in each stage, the creation of high n ⁺ source and drain-regions of elementary cells in the high-resistance p ^- -layer substrate by introducing arsenic ions into the substrate when used as a protective mask and the polysilicon gate electrode layers of photoresist and the subsequent diffusive redistribution of the implanted impurities, the formation of metal screens, drain electrodes and a shutter of unit cells on the front side of the substrate and the common metal electrode the source of the transistor structure on its back side, characterized in that after the creation of p-pockets, the gate dielectric between the polysilicon electrodes of the gate of the unit cells is thinned to a thickness of 100-300 Å, the first protective layer of the photoresist is applied to the front side of the substrate, two windows are opened simultaneously in the photolithography method the first protective layer of the photoresist, respectively, at the location of the highly doped n ⁺ -regions of the drain and the source of unit cells and introduce phosphorus ions through them into the substrate with a dose of 0.2-0.6 μC / cm ² and with an energy of 80-140 keV and arsenic ions with a dose of 400-500 μC / cm ² and an energy of 40-80 KeV, then the second stock window in the second protective layer of the photoresist bordering the first stock window around the periphery and through the second stock is opened by photolithography a window is implanted with phosphorus ions with the same dose and energy as in the first stock window, then the third stock window in the third protective layer of the photoresist, bordering the second stock window around the periphery, is opened by photolithography, and phosphorus ions are introduced into the substrate through the third stock window ora with a lower dose and energy than in the second stock window, then in a similar manner the subsequent steps of lightly doped n ^- regions of the runoff of unit cells are formed, moreover, in each next step phosphorus ions are implanted with a lower dose and energy compared to the previous one, after which the residues are removed the protective layer of the photoresist on the front side of the substrate and conduct simultaneous diffusion acceleration of impurities of phosphorus and arsenic embedded in the substrate.

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