RU2002123376A - Носимый носитель данных - Google Patents

Носимый носитель данных

Info

Publication number
RU2002123376A
RU2002123376A RU2002123376/09A RU2002123376A RU2002123376A RU 2002123376 A RU2002123376 A RU 2002123376A RU 2002123376/09 A RU2002123376/09 A RU 2002123376/09A RU 2002123376 A RU2002123376 A RU 2002123376A RU 2002123376 A RU2002123376 A RU 2002123376A
Authority
RU
Russia
Prior art keywords
chip
carrier according
places
given bend
semiconductor chip
Prior art date
Application number
RU2002123376/09A
Other languages
English (en)
Other versions
RU2234130C2 (ru
Inventor
Юрген ФИШЕР (DE)
Юрген ФИШЕР
Манфред ФРИС (DE)
Манфред Фрис
Франк ПЮШНЕР (DE)
Франк ПЮШНЕР
Аннемари ЗАЙДЛЬ (DE)
Аннемари ЗАЙДЛЬ
Original Assignee
Инфинеон Текнолоджиз Аг (De)
Инфинеон Текнолоджиз Аг
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=8167756&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=RU2002123376(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Инфинеон Текнолоджиз Аг (De), Инфинеон Текнолоджиз Аг filed Critical Инфинеон Текнолоджиз Аг (De)
Publication of RU2002123376A publication Critical patent/RU2002123376A/ru
Application granted granted Critical
Publication of RU2234130C2 publication Critical patent/RU2234130C2/ru

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Claims (8)

1. Носимый носитель данных, содержащий картообразное тело (1), имеющее углубление (2) для размещения чип-модуля (3), причем чип-модуль (3) включает в себя, по меньшей мере, один полупроводниковый чип (4) на первой главной стороне (5) держателя (18) чипа, соединенного с картообразным телом (1), и содержащую контактные выводы (8) металлизацию (7) на второй главной стороне (6) держателя (18) чипа, отличающийся тем, что держатель (18) чипа имеет места (9) заданного изгиба, лежащие в пределах боковых кромок (12) углубления (2).
2. Носитель по п.1, отличающийся тем, что места (9) заданного изгиба лежат вне полупроводникового чипа (4).
3. Носитель по п.1 или 2, отличающийся тем, что места (9) заданного изгиба лежат вне охватывающего полупроводниковый чип (4) покрытия (10).
4. Носитель по одному из пп.1-3, отличающийся тем, что места (9) заданного изгиба образованы, по меньшей мере, одной прорезью (13) в каждом контактном выводе (8), которая разделяет соответствующий контактный вывод (8) на первую (14) и вторую (15) зоны.
5. Носитель по п.4, отличающийся тем, что первая (14) и вторая (15) зоны соединены между собой, по меньшей мере, одной перемычкой.
6. Носитель по п.4 или 5, отличающийся тем, что прорези (13) проходят в направлении, в котором контактные выводы (8) лежат по соседству друг с другом.
7. Носитель по одному из пп.4-6, отличающийся тем, что перемычки (16) имеют значительно меньшую ширину, чем, по меньшей мере, одна прорезь (13).
8. Носитель по одному из пп.1-3, отличающийся тем, что металлизация (7) заканчивается в пределах мест (9) заданного изгиба.
RU2002123376/09A 2000-02-02 2001-01-15 Носимый носитель данных RU2234130C2 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00102073.4 2000-02-02
EP00102073A EP1122685B1 (de) 2000-02-02 2000-02-02 Chipkarte mit Sollbiegestellen

Publications (2)

Publication Number Publication Date
RU2002123376A true RU2002123376A (ru) 2004-02-20
RU2234130C2 RU2234130C2 (ru) 2004-08-10

Family

ID=8167756

Family Applications (1)

Application Number Title Priority Date Filing Date
RU2002123376/09A RU2234130C2 (ru) 2000-02-02 2001-01-15 Носимый носитель данных

Country Status (9)

Country Link
US (1) US6778407B2 (ru)
EP (1) EP1122685B1 (ru)
JP (1) JP4284021B2 (ru)
CN (1) CN1213386C (ru)
AT (1) ATE404941T1 (ru)
DE (1) DE50015305D1 (ru)
ES (1) ES2312310T3 (ru)
RU (1) RU2234130C2 (ru)
WO (1) WO2001057793A1 (ru)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10208172B4 (de) * 2002-02-26 2005-07-07 Infineon Technologies Ag Zwischenträger zum Einsetzen in einen Träger und Träger mit einem Zwischenträger
JP4103653B2 (ja) * 2003-03-27 2008-06-18 株式会社デンソー Ｉｃカード
US7556746B2 (en) * 2004-06-03 2009-07-07 Nantero, Inc. Method of making an applicator liquid for electronics fabrication process
US7911699B2 (en) * 2005-12-22 2011-03-22 Guardian Industries Corp. Optical diffuser with UV blocking coating
DE602005013807D1 (de) * 2005-12-30 2009-05-20 Incard Sa IC Karte mit verbesserter Leiterplatine
EP1804201B1 (en) * 2005-12-30 2009-05-13 Incard SA Module for an IC card
US7850468B2 (en) * 2007-06-28 2010-12-14 Super Talent Electronics, Inc. Lipstick-type USB device
WO2010040645A2 (de) * 2008-10-08 2010-04-15 Osram Gesellschaft mit beschränkter Haftung Schaltungsträger
TWM362572U (en) * 2009-04-13 2009-08-01 Phytrex Technology Corp Signal convertor
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
CN104182793B (zh) * 2014-08-28 2017-03-08 绵阳市绵州通有限责任公司 一种自调式抗扭曲公交卡
US10410996B2 (en) * 2016-12-02 2019-09-10 Dialog Semiconductor (Uk) Limited Integrated circuit package for assembling various dice in a single IC package
DE102021001814A1 (de) 2021-04-08 2022-10-13 Giesecke+Devrient Mobile Security Gmbh Chipmodul und Chipkarte

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2580416B1 (fr) * 1985-04-12 1987-06-05 Radiotechnique Compelec Procede et dispositif pour fabriquer une carte d'identification electronique
FR2634095A1 (fr) * 1988-07-05 1990-01-12 Bull Cp8 Circuit imprime souple, notamment pour carte a microcircuits electroniques, et carte incorporant un tel circuit
JPH0230598A (ja) * 1988-07-20 1990-01-31 Dainippon Printing Co Ltd Ｉｃモジュールおよびｉｃカード
FR2639763B1 (fr) * 1988-11-29 1992-12-24 Schlumberger Ind Sa Procede de realisation d'un module electronique et module electronique tel qu'obtenu par ce procede
DE4406704C1 (de) * 1994-03-02 1995-07-20 Angewandte Digital Elektronik Chipkarte
DE4443767A1 (de) * 1994-12-08 1996-06-13 Giesecke & Devrient Gmbh Elektronisches Modul und Datenträger mit elektrischem Modul
DE19710144C2 (de) * 1997-03-13 1999-10-14 Orga Kartensysteme Gmbh Verfahren zur Herstellung einer Chipkarte und nach dem Verfahren hergestellte Chipkarte

Also Published As

Publication number Publication date
JP4284021B2 (ja) 2009-06-24
DE50015305D1 (de) 2008-09-25
US6778407B2 (en) 2004-08-17
ES2312310T3 (es) 2009-03-01
JP2003521787A (ja) 2003-07-15
WO2001057793A1 (de) 2001-08-09
ATE404941T1 (de) 2008-08-15
EP1122685A1 (de) 2001-08-08
CN1397048A (zh) 2003-02-12
CN1213386C (zh) 2005-08-03
RU2234130C2 (ru) 2004-08-10
US20030016507A1 (en) 2003-01-23
EP1122685B1 (de) 2008-08-13

Similar Documents

Publication Publication Date Title
RU2002123376A (ru) Носимый носитель данных
US5973935A (en) Interdigitated leads-over-chip lead frame for supporting an integrated circuit die
US6344976B1 (en) Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die
US5229960A (en) Solid state memory modules and memory devices including such modules
RU97105188A (ru) Несущий элемент
RU2004112774A (ru) Чип-карта с дисплеем
DE59504284D1 (de) Trägerelement für integrierten schaltkreis
ES2123342T3 (es) Tarjetas de chip sin contacto.
WO2004064110A3 (en) Space-efficient package for laterally conducting device
EP0408779A1 (en) High density semiconductor memory module
RU99115169A (ru) Несущий элемент для полупроводникового кристалла, предназначенный для встраивания в карточку с интегральными схемами
EP0987749A3 (en) Semiconductor device, electrode structure therefore, and production thereof
US6052289A (en) Interdigitated leads-over-chip lead frame for supporting an integrated circuit die
ATE319203T1 (de) Elektrischer verbinder für eine chipkarte mit grosser speicherkapazität
DE50005564D1 (de) Chipkartenanordnung
JP3108536B2 (ja) Ｉｃメモリカード
JPH03116860A (ja) 半導体装置
US6927094B2 (en) Method for assembling a semiconductor chip utilizing conducting bars rather than bonding wires
DE29720384U1 (de) Mini-Chipscheibe, funktionsgleich einer wechselbaren kleinstformatigen Halbleiter-Speicherkarte für Telekommunikationsgeräte
JP3121042B2 (ja) Ｉｃモジュールおよびｉｃカード
JPH04137754A (ja) リードフレーム
FR2855891B1 (fr) Module a carte a puce
JPS62248695A (ja) 薄形半導体カ−ド
KR930018579A (ko) 초박형 메모리 모듈
KR970024101A (ko) 다이 패드의 슬릿(slit)내에 내부 리드가 설치된 리드 프레임

Legal Events

Date Code Title Description
MM4A The patent is invalid due to non-payment of fees

Effective date: 20090116