RU1815636C - Device for microprogram control - Google Patents

Abstract

The invention relates to computing and may find application in the creation of central processing units. The aim of the invention is to increase the speed of the device. The device comprises a local control unit, an OR-NOT element, an address counter, a cycle counter, a zero driver, a microprogram address stack, an address switch, an executive address register 8, a micro memory instruction block, a micro instruction register. 4 ill., 2 tablets

Description

The invention relates to computer technology and can be used to create central processors, for example, for generating and reading the address of the next microcommand.

The aim of the invention is to increase the speed of the device.

In FIG. 1 is a functional diagram of a firmware control device.

The device contains a local control unit 1, an OR-NOT 2 element, an address counter 3, a 4-cycle counter, a zero-signifier 5, a stack of 6 firmware addresses with a stack pointer, an address switch 7, an executive address register 8, a micro-instruction memory unit 9, a register 10 microcommands, in addition, the drawing shows the input 11 of the modification (transfer input to the counter 3 addresses) of the device address, input 12 of the device synchronization, input (first) 13 of the initial installation of the device, input 14 (14.1. 14.2, 14.3 ... 14.1) device addresses, input 15 device transition condition, code 16 initial setting (reset), codes 17.1 and

Stack control 17.2, switch control codes 18.1 and 18.2 of switch 7, microcontrol register register enable code 19, second input (code) 20 of the initial setup, codes 21.1. and counter control 21.2, output 22 of the sign for setting the device start address, output 23 of the request sign of the device interrupt vector, information output 24 of the counter 3, information output 25 of the counter 4, information output 26 of the stack 6, output 27 of the signifier zero (sign code resetting the counter 4), information output 28 of switch 7, information output 29 of register 8, information output 30 (microcommand) of block 9, output 31 field (code) of register address 10, output 32 field of code of the analyzed condition of register 10, output 33 (33.1, 33.2 ... 33.0 half m natural control (microproducts) of register 10. output 34 of the sign of recording the address, output 35 + the stack is full, output 36 is the floor (code) of the device's microoperations.

The cycle counter (figure 2) contains (for the four-bit version) elements And 36,

ate

with

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ate about

00

about

37, 38, 39, 41, 42, 43, elements excluding OR 44, 45, 46, 47, elements OR 40, 48,49,50, 51, trigger 55, 56,57,58, elements OR NOT 52, 53, 54, data inputs 14.1, 14.2, 14.3, 14.4, inputs 21.1 and 34 of the sign of writing the address to the counter, input of the sign of reading address 21.2, synchronization input 12, initial setting input 16, direct outputs of flip-flops 25.1, 25.2.25 ..4.06- trigger outputs, 25.1, 25.2, 25.3 and 25.4.

The address counter (FIG. 3) contains (for the four-bit version) elements exclusive OR 59, 61, 63, 65, elements 60, 62, 64, 66, D-flip-flop 68, 69, 70, 71 (68 is the least significant d, 71 - senior bit), information inputs 28.1, 28.2, 28.3, 28.4, transfer input 11, (address modification), transfer output 72, clock input 12, initial setup input 16, information outputs of the address counter 24.1, 24.2, 24.3, 24.4.

The local control unit (Fig. 4) for a four-bit microcommand code contains OR elements 73, 75, 77, 81, 83, 85, 87, 94, OR element groups 79, 89, 91, AND 95 element, OR-NOT 74 elements , 76, 78, 80.82.84.86.88.90.90, decoder 93. input (code) 27 counter zeroing signs 4. input 32 code of the analyzed condition, input (code) 15 device transition condition, inputs (codes) 33.1, 33.2. 33.3, 33.4 field of local control (micro-orders), output (code) 20 of the initial installation, outputs (codes) 32-1.1. And 21.2 control of the counter 4, output (code) 22 sign of setting the start address, output (code) 23 sign of request for vector interrupts, an output (code) 19 for enabling reading of the register of microcommands 10, outputs (codes) 17.1 and 17.2 for managing the stack 6. outputs (codes) 18.1 and 18.2 for controlling the switch 7.

Register 8 of the executive address is built as a standard register.

The numbering of elements, external inputs and outputs of the cycle counter, address counter and local control unit is done taking into account the numbering of the blocks, inputs and outputs of the microprogram control device (see Fig. 1, Fig. 2, Fig. 3, Fig. 4 together).

The device operates as follows.

Each micro-command stored in the micro-memory block 9 contains an address and a control part. The address part of the microcommand contains the address code 31 of the next microcommand. The control part of the microcommand contains the microcode sequence 33.1, 33,2, 33.1 ... 33.1, which are issued when the current microcommand is executed in the form of a code combination, the code 32 of the condition being analyzed, the code 34 of the flag for writing the address to the 4-cycle counter, and the microoperation control code 36 .

The operation of the device can be divided into two stages and means: the first (main) stage and means - forming the address of the next microcommand, the second stage and means - storing the executive address, storing and reading the microcommand.

Consider the step of generating the address of the next microcommand. The address is formed from two sources: internal and

5 external.

The internal sources are: register of 10 micro-instructions, counter 3 addresses, counter 4 cycles, stack 6 addresses of firmware. External sources may be

0 start address decoder and interrupt vector decoder.

Consider the purpose of the means for forming the address of the next microcommand.

5 The local control unit is built as a logic matrix. Local control unit 1 (for a four-bit microcommand code) with a code combination of 33.1, 33.2, 33.3 and 33.4 micro-orders, code 15,

0 code 27 and code 32 generates simultaneously control codes: stack control codes 17.1, 17.2 6, switch control codes 18.1 and 18.2 7, counter control codes 21.1 and 21.2 4, initial code 20

5 settings and one of three codes: 19 (permission to read register 10), 23 (sign of requesting the interrupt vector), 22 (sign of setting the start address).

The following are tables 1 and 2 of truth

0 the decoder of the local control unit and this local control unit for the case of a four-bit microcode.

The cycle counter works in the following

5 modes: data recording mode (the recorded data can be addresses or the number of cycles), signal O is sent to input 21.1 or 34, and input 21.2. signal 1 is given. Through elements And 36, 37, 38, 39

0 and OR 48, 49, 50, 51 input data is written to flip-flop 55, 56, 57, 58 at a positive edge of the clock signal.

Countdown mode (the counter works as a subtracter): input 21.1 (or 34)

5, signal 1 is supplied. Signal O is applied to input 21.2. The signal O is set at the outputs of the AND 36, 37, 38, 39 elements. At the same time, the output of the OR 40 element is set to 1, and the signal conjunction is established at the outputs of the AND 41 elements. 42, 43 from the reverse outputs of the triggers 55, 56, 57. Due to the fact that the direct outputs of the triggers 55, 56, 57. 58 are connected to the first inputs of the elements exclusive OR 44, 45. 46, 47 and the outputs of the element OR 40, elements AND 41 , 42, 43 connected to the second inputs of the elements exclusive OR 44, 45. 46, 47 summed by mod 2 the value of the signals through the elements OR 48, 49. 5 0, 51 goes to the D-inputs of flip-flops 55, 56, 57, 58 and is recorded on the positive edge of clock signal 12. Storage mode: to input 21.1. (or 34) and 21.2 signal G. is output. At the output of AND 36, 37, 38, 39, 41, 42, 43 and OR 40 elements, the value of signal O. Through exclusive OR elements 44, 45, 46, 47 (modular summation 2) and OR 48, 49, 50.51 signals from the direct outputs of flip-flops 55, 56, 57, 58 are fed to the D-inputs of flip-flops 55, 56. 57. 58 and this ensures the storage of information previously recorded in flip-flops 55, 56, 57.58.

The zero flag generator 5 generates a nullification flag code 27 (positive signal) only when the code 25 is zero (i.e., the contents of counter 4 are zero).

The address counter works as follows.

The mode of increasing the address (data) by 1. In this mode, the transfer code 11 should be 1. Then, depending on the input data (codes) 28.1, 28.2, 28.3 and 28.4, the exclusive codes OR 59, 61, 63, 65 are set at the output of the elements, increased by 1 and therefore at the D-input of flip-flop 68. 69, 70, 71 also sets the corresponding state at a positive edge of clock signal 12. At transfer output 72, code 1 is set only when at inputs 28.1, 28.2, 28.3. 28.4 and 11 are set to state 1.

Data storage mode. In this mode, the transfer code 11 must be O, then with a positive edge of the clock signal 12, the triggers 68, 69, 70, 71 record codes 28.1, 28.2, 28.3, 28.4 without changes.

Stack of 6 firmware addresses - memory with stack pointer. Stack 6 is designed to store the return address when executing firmware and works on the principle - the last is written - the first is read. Stack 6 provides for writing, storing and reading the address code 24 generated in the counter 3. When writing information, the stack pointer increases by one, when reading decreases by one. The nesting depth of the firmware depends on the size of the stack pointer. When the last cell of the stack is filled, a code 35 is generated. The stack is full. Writing and reading information (i.e., code 24 and code 26) on the stack 6 occurs by the presence of code 12 (positive edge of the clock signal).

Switch 7 addresses provides a choice of four received at its inputs

0 address codes: address code 14 (either from the register of 10 microcommands or from external sources), address code 24 (generated in counter 3), address code 25 (generated in counter 4) and address code 26 (generated in stack 6) . Code 28 enters the counter 3 addresses and in the register 8 of the executive address.

Consider the second stage and storage means of the executive address, storage and

0 read microcommands.

The executive address register 8 provides storage of the address code 28 and transmission of the executive address code 29 to the micro-instruction memory unit 9. Block 9 memory

5 of the microcommands is constructed so that it decrypts the executive address code 29 and transmits the microcommand 30, stored in the memory of block 9 to the register 1, of the microcommands. Register 10 microcommands provides

0 recording, storing and issuing a micro-command (corresponding codes 31. 32, 33.1, 33.2, 33.3, 33.4,34 and 36) to form the address of the next micro-command and perform microoperations,

5 It is necessary to note the formation of the zero address, i.e., the address of the micro-command located at the zero address in block 9 of the micro-command memory. The zero address is formed in two ways: by input

0 (first) 13 initial installation of the device (negative signal) and the second input (code) 20 of the initial installation (negative signal). Code 20 is generated (negative signal) by local unit 1

5 controls if at its input a combination of 33.1. 33.2, ЗЗ.З ... ЗЗ-i has a zero value, i.e. 0,0 ... 0. Thus, if one of the two codes 13 or 20 (a negative signal) is present, the OR-NOT 2 element generates a code 16 (positive signal) which nullifies counter 3, stack 6, counter 4, register 8, and therefore the executive address code 29 provides reading a micro command at the zero address of block 9

5 memory microcommands.

Using this device makes it possible to form the address of the next microcommand from external and internal address sources; perform a hardware reset and therefore

reading a micro instruction located at the zero address of the micro memory instruction block; storage of executive address; recording, storage and sequential sampling of a micro command at an executive address; combining the operations of forming an address and reading microcommands of various steps.

Claims (1)

The claims A microprogram control device comprising a local control unit, a micro memory command block, an address counter, a zero generator, a micro register, a microprogram address stack, a cycle counter, an address switch, and the synchronization inputs of the micro register, address counter, cycle counter and microprogram stack are connected to the device input of the same name, the information input of the cycle counter, the first information input of the address switch and the output address field of the micro-command register are connected to the hell input When the device is in, the address counter transfer input is the input of the device address modification, the transition condition input of the local control unit is the device input of the same name, the first output of the local control unit is the output of the sign indicating the start address of the device, the second output of the local control unit is the output of the request sign device interrupt vector output Stack full of the microprogram address stack is the device output of the same name, the third output of the local control unit is connected to the control exhibiting an inlet stack firmware addresses fourth local control unit output is connected to a control input of the counter cycles, the fifth output of the local control unit is connected to the control input of the switch address information output address counter coupled to the data input of the address stack firmware and a second data input address switch, the information output of the microprogram address stack is connected to the third information input of the address switch, the output of the loop counter is connected to the fourth information the input of the address switch and with the information input of the generator of the sign of zero, the output of which is connected to the first control input of the local control unit, the output of the micro-command memory unit connected to the information input of the micro-command register, the output of the analyzed condition code field is connected to the second control input of the local control unit, the third control input of which the local control field of the micro-command register is connected to the output, the input sign of the address record of which is connected to the recording counter input of the cycle, the sixth output of the local control unit is connected with an enable input for reading the register of microcommands, the output of the microoperation field of which is the device output of the same name, characterized in that, in order to improve performance, the device contains an executive address register and an OR-NOT element, the first and second inputs of which are connected respectively to the initial installation input of the device and the seventh output of the local control unit, the output of the OR element is NOT connected by Ј inputs of the initial setting of the address counter, microprogram address stack, cycle counter and register ceiling elements addresses, the clock input, the data input and output of which are connected respectively to the input device synchronization switch output address and an address input of the memory block of microinstructions. Truth table decoder block 1 local government Table 1 Continuation of table 1 Truth Table of Local Government Unit 1 Continuation of table 1 TeBlitz2 Continuation of table 2