JPS6121694Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a general-purpose register reading device in a microprogram-controlled information processing device.

Generally, general-purpose registers are used as accumulators when performing arithmetic and logical operations.
Used as a base address register or index register when generating operand addresses.

Figure 1 shows an RX-format macro instruction, where OP is an operation field, R is a general-purpose register specification field, X is an index register specification field, B is a base register specification field, and D is a displacement field. Each represents a mate field. When generating an operand address, the contents of the general-purpose register, or index register, specified by the X field, X, and B
The contents B of the general-purpose register, that is, the base register specified by the field, and the value D of the D field are added in binary. As an exception, when the value of the X field is zero, it is specified that the index register is not used, and when the value B of the B field is zero, it is specified that the base register is not used.

In the prior art, operand addresses were generated according to a flowchart such as that shown in FIG. In the prior art, a microinstruction is used to determine whether the X field is zero or the B field is zero, which has the disadvantage that it takes a long time to generate an operand address.

SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks and provides a register reading device that can reduce the time required to generate operand addresses. Therefore, the register reading device of the present invention is
In a register reading device that includes a group of general-purpose registers and an addressing register that addresses them, and reads out a general-purpose register specified by address information from the addressing register, address information in the addressing register is provided. a zero determination circuit that determines whether or not data indicates a zero value; a microinstruction storage register that stores microinstructions; and data modification means that modifies the readout output of the general-purpose register; The means outputs data indicating a zero value when the address information in the addressing register has a zero value and a specific bit of the microinstruction in the microinstruction storage register has a specific value; In other cases, the readout output of the general-purpose register is output as is. Hereinafter, the present invention will be explained with reference to the drawings.

Figure 3 is a block diagram of an embodiment of the present invention;
The figure is a flowchart for generating operand addresses using the present invention.
In FIG. 3, 1 is a register for address designation, 2 is a zero determination circuit, 3 is an address information line, 4,
5, 6, and 7 are signal lines, 8 is a microinstruction storage register, 9 is a general-purpose register group, 10 is an AND circuit, 11 is a read output line, and 12 is a NAND circuit.

When generating an operand address, a microinstruction is used in which a specific bit of the microinstruction is logic "1". At this time, the value B of the B field and the value X of the X field of the microinstruction are set in the addressing register 1.

Since the specific bit P of the microinstruction stored in the microinstruction storage register 8 is logic "1", the signal line 5 becomes logic "1". Now, suppose that value X is read from addressing register 1,
In addition, the read signal, that is, the address information is all
Suppose it is zero. In this case, the zero determination circuit 2 outputs a logic "1" to the signal line 4, and the NAND circuit 12 outputs a logic "0" to the signal line 6. As a result,
All AND circuits 10 output logic "0". The all-zero address information specifies the 0th general-purpose register in the general-purpose register group 9, and an output is generated on the signal line 7, but this output is invalidated. If the value B of the B field of the macro instruction is read from the addressing register 1 under the state where the specific bit P is logic "1" and the value B is all zeros, the read output line 11
becomes all zero.

In cases other than when generating an operand address, for example, when performing an operation using a general-purpose register, a microinstruction in which a specific bit of the microinstruction is logic "0" is used. At this time,
The output of the general-purpose register designated by the address information line 3 appears as is on the read output line 11.

Figure 4 shows a flowchart for generating operand addresses when using the present invention.As can be seen from this figure, when a general-purpose register is specified by the value A value obtained from the read output line 11, and a value obtained from the read output line 11 when a general-purpose register is specified with the value B of the B field of the macro instruction.
By simply adding the displacement D, the operand address is generated.

As is clear from the above explanation, by using the present invention, it is possible to use a microinstruction to determine whether the contents of the index/register specification field of a macroinstruction are zero or the contents of the base register specification field are zero. As a result, the operand address can be generated without
The time required for address generation can be shortened.

[Brief explanation of the drawing]

Figure 1 shows RX format macro instructions, Figure 2
The figure shows the conventional operand address generation flow.
FIG. 3 is a block diagram of one embodiment of the present invention, and FIG. 4 is a flow chart of operand address generation when the present invention is used. 1... Address designation register, 2... Zero determination circuit, 3... Address information line, 4, 5, 6, 7...
...Signal line, 8...Micro instruction storage register, 9
...General-purpose register group, 10...AND circuit, 11
...Readout output line, 12...NAND circuit.

Claims (1)

[Scope of utility model registration request] In a register reading device that includes a group of general-purpose registers and an addressing register that addresses them, and reads out a general-purpose register specified by address information from the addressing register, address information in the addressing register is provided. a zero determination circuit that determines whether or not data indicates a zero value; a microinstruction storage register that stores microinstructions; and data modification means that modifies the readout output of the general-purpose register; The modifying means outputs data indicating a zero value when the address information in the addressing register has a zero value and a specific bit of the microinstruction in the microinstruction storage register has a specific value; A register reading device characterized in that it is configured to output the readout output of a general-purpose register as is in other cases.