RU1805503C - Self-testing memory gate - Google Patents

Abstract

The invention relates to the field of computing, in particular to memory devices. The aim of the invention is to increase the reliability of the device. A memory device with autonomous control comprises an address accumulator, an input register, coding and correction blocks, first and second output registers, first and second associative drives, an analysis unit, first to third switches, a comparison unit, an address signal generator, adders modulo two, OR element group and control unit. Three types of operations can be performed on the device: reading, writing, monitoring. When data is read in the second associative drive, the addresses of the cells from which the error word is read are fixed. During monitoring, the selection of failures and failures, determination of the type of failure of the discharge of the cell, and coordination of the type of failure with the value of the recorded symbol are carried out. 3 ill. 2 tab. ate with

Description

The invention relates to computer technology and can be used to create storage devices based on integrated storage devices.

, The purpose of the invention is to increase the reliability of the device by efficiently utilizing the capacity of the associative drive.

In FIG. 1 shows a block diagram of a device; in FIG. 2 is one embodiment of a control unit; in FIG. 3 - one of the variants of the second associative drive.

The device contains a drive 1, to the address 2 inputs of which are connected the outputs of the driver 3 address signals, to the information 4 inputs of the drive 1 are connected the outputs of the input 5 register having an additional 6 bits, the first 7 inputs of the input register 5 are connected to the outputs of the first 8 switch and the inputs of the block 9 coding, the outputs of which are connected to the second 10 inputs of the input register, the first inputs of the first 8 register are information 11 inputs of the device. The inputs of the address signal driver 3 are connected to the outputs of the second 12 switch, the first inputs of which are the address 13 inputs of the device.

The device also contains first 14 and second 15 output registers, correction unit 16, modulo two adders 17, control unit 18, first 19 associative storage, having an argument part 20 for storing the addresses of the failed cells of the accumulator 1, a test part 21 for storing the idle bit number and the functional 22 part for storing the type of failure of an inoperative discharge, the second 23 associative drive, having

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the argument part 24 with the comparison circuit and the control part 25, the third switch 26, the comparison unit 27, the analysis unit 28 containing the AND elements 29 and the OR elements 30, and the group of 31 OR elements. The second output 15 register has an additional 32 bits, the outputs of the information 33 bits of the register 15 are connected to the first inputs of the correction unit 16, the second inputs of the adders 17 modulo two, and the second inputs of the analysis unit 28; the outputs of the control 34 bits are connected to the second inputs of the correction unit 16. The first 35 outputs of the correction block 16 are connected to the first inputs of the adders 17, the first inputs of the analysis block 28 and the inputs of the group of 31 OR elements, the second 36 outputs of the correction block 16 are connected to the inputs of the attribute 21 of the first 19 associative drive, the inputs of the functional part are connected to the output of block 28 analysis, the inputs of the argument part 20 are connected to the outputs of the driver 3 and the inputs of the argument 24 of the second 23 associative drive, address 37 outputs of which are connected to the second 38 inputs of the second 12 switch. The outputs of the first 14 output register are connected to the second inputs 39 of the first 8 switch and are information outputs 40 of the device.

The first 41 control input 18 is connected to the control output of the first 19 associative drive, the second 42 and third 43 inputs of the control unit 18 are connected to the control outputs of the second 23 associative drive, the fourth 44 input is connected to the output of the comparative unit 27, the fifth 45 input connected to the output of the group of 31 elements OR, the sixth 46 input is connected to the output of the additional 32 bits of the register 15. The seventh 47, eighth 48 and ninth 49 inputs of the control unit are the control inputs of the device, the first 50 output of the unit 18 is the control output th device 51 outputs the second connected switch inputs kupravl yuschim blocks of registers and storage devices.

The first 19 associative drive is intended for storing the addresses of the cells of the drive 1 with failed bits, the numbers of the failed bits and the type of failures,

The second 23 associative drive is intended for storing the addresses of the cells of the drive 1 from which the code words with the first errors are read, caused by a malfunction or failure. The storage of these addresses of the cells of the accumulator 1 is carried out in the argument part 24.

The control unit 18 contains a 14-bit shift register 52, a clock generator 53, input elements AND 54 ... 61, input elements OR 62 ... 65, output elements 66 AND, output elements 67 AND-OR, elements 68 NOT . The inputs 47 ... 49 of the control unit 18, which are the control inputs of the device, receive potential signals that specify the operating mode of the device. The signal at input 47 sets the recording mode, at input 48, the mode. reading, at input 49 - control mode. At

5 received at the inputs 47 .. 49 of one of these signals, the clock generator 53 is started, generating the shift signals of the register 52. Signals are sent to the inputs 41 ... 46 of the block 18, notifying the results of the operation of the device. The conditions for the occurrence of these signals are listed in Table. 1.

Table 2 shows the purpose of the output signals of block 18.

5 In FIG. Figure 3 shows a possible technical implementation of the second associative drive 23 comprising an argument part 24 with a comparison circuit and a control part 25 (see Fig. 1). The argument part 24 consists of a drive 69 for storing the N x n addresses of drive 1, a drive 70 for storing occupancy bits of the cells of drive 69, and a comparator 71 containing bitwise comparison schemes and a comparison result display register. The technical implementation and operation of the comparison circuit are given in the literature (3). The control part 25 contains an associative register 72

0 signs, input 73 and output 74 registers, first 75, second 76, third 77 and fourth 78 elements OR, first 79 and second 80 elements AND, element NOT 81 and former driver 82

5 or the first free cell.

The operation of the second associative storage device 23 is carried out according to the output signals of the control unit 18. When reading (upon receipt of signal Y15) from the output of block 3 through the register 72, an associative sign arrives at the comparison circuit 71 - the n-bit address of drive cell 1. If this address matches the bit address stored in accumulator 69, it will be established to a single state, the corresponding bit of the display register block 71 (see lit. (3)). In this category, the output 37 of associative drive 23 will receive an n-bit address read from drive 69. If there is a mismatch

of addresses by the write signal U 16 through register 73 to drive 69, into the first free cell, the n-bit address received from the output of block 3 is recorded. Shaper 82 will issue the address of the first free cell and allow the issuance of recording information from register 73.

In the Monitoring mode, when making requests for the occupancy of the cells of the second associative storage (signal Y18), the contents of the occupation bits are checked. If all occupancy bits are in the zero state, i.e., all cells of the accumulator 69 are free, then signal X3 is generated (the second 23 associative accumulator is empty). If at least one busy bit is in a single state, then the address of the first occupied cell of the drive 69 to be read is generated in the address generator 82. The formation of the address is carried out on the principle of shifting the information received at the input of the address generator 82, while counting the number of shifts. The read contents of the first occupied cell through the register 74 will go to the output 37 of the associative drive 23.

The logic diagram of the algorithm of the device has the form:

1) RFP Y1 Y2 Y3 X1Y4 Y5 Y4 X4 (Y7 Y6) Y8 YO;

2) Midrange Y1 Y9 Y10X6 (Y11 Y12 Y13) Y14X 5 (Y3X1 Y15X2 Y16) Y17 YO;

3) YO KHTP Y18X3 Y19 Y9 Y10 (Y12 Y13) X5Y14 (Y20Y17) Y21 Y3 Y4 Y5 X4 Y6 Y8 YO.

The device operates as follows.

In the initial state, the registers 5, 15, 14 are zeroed, the zero bit of the shift register 52 is set to one, the bits 1 .. 13 of the register 52 are set to the zero state. In the recording mode, the input 47 of the device receives a single potential signal, which, through the OR element 65 (Fig. 2), triggers the clock generator 53, which ensures, by shifting the unit in the register 52, the formation of control signals Yi (where i 0,1 ... 21 )

The address 13 of the device (Fig. 1) receives the address of the address, which, according to the signal Y1 of the control unit 18, is supplied through the second 12 switch to the driver 3 of the address signals.

The written codeword containing k-bits is fed to the information input and, according to the Y2 signal, through the first 8 switch to the input 5 register and coding block 9, formed in the block of r-control bits 9 in accordance with the correction code used, for example, the Hamming code also go to input register 5. Thus, k-information and r-control bits (k + rn) are stored in input 5 register, a

also a zero value in additional bit 6 of register 5.

By signal Y3, the address of access from the shaper 3 goes to the first 19 associative drive, in which

0, an associative search is in progress.

If the argument part 20 of the drive 19 contains an address that matches the address of the address, then a single signal 5 (X1 1) is generated at the control output of the drive 19, which arrives at the first 41 input of the control unit 18 and does NOT close one of the inputs through element 68 element And 60. This ensures the formation at the outputs 51 of the block 18 of the control signals Y4 and Y5. By signal Y4, the code word (k-bits) from the direct outputs of the input 5 register is supplied to the second inputs of the third 26 switch. The switch 26 extracts from one word the corresponding bit, the number of which is indicated in the attribute part 21 of the drive 19, and transfers to the input of the comparison unit 27. Block 27 compares the value of the bits with the contents of the functional part (by signal Y5). The result of the comparison X4 is supplied to the fourth 44 input of the control unit 18 and provides the formation of either a signal Y6 or Y7. If the comparison occurred (X4 I), i.e., the type of failure in the drive unit 1 is consistent with the bit value of the code word, then the word (n + 1 bits) is written to drive 1 in the direct code from the input 5 register (control signals Y7 and Y8). If the coincidence is not

0 occurred (X4 0), i.e., the type of failure is not consistent with the value of the codeword bit, then the codeword in the reverse code (control signals Y6n Y8) is written to drive 1, while in (n + 1) an additional 5th digit of a given cell is written to a unit value. A single value of the (n + 1) th additional digit indicates that the code word is written in the reverse code in this drive cell.

0 If, however, in any cell of the first associative drive 19 there is no address that matches the address of the address, i.e., X1 0, then the code word is written to drive 1 in the direct code. (The warning signal X1 0 is supplied to the first 41 input of the control unit 18 and through element 68-NOT opens one of the inputs of element 60 I. The single signal from input 47 is supplied to the second input of element 60 And the single signal from output O is received to the third 3 registers 52

shift, which will ensure that the third digit of register 52 is set to zero and the sixth digit is set to unity. Thus, signals Y4, Y5, Y6 are not generated, and only signals Y7 and Y8 are generated.

After writing the code word to the drive 1 in the control unit 18 (Fig. 2), a single signal from the output 0 of 8 register 52 through the element 55 And sets the eighth bit to zero and to the unit - the zero bit, from the output of which to the output 50 the device is given a signal that the device is ready to execute another command.

In the read mode, a single potential signal is supplied to the input 48 of the device, which, similarly to the write mode, triggers the control unit 18. The access address is from input 13, by signal Y1 through the second 12 switch and driver 3 is fed to address 2 of the inputs of drive 1. Drive 1 is started (by signal Y9) to read the code word, which is received (by signal Y10) to the second 15 output register. Depending on the value of the (n + 1) th additional 32 bit of register 15, a forward (X6 - 0, Y11 signal) or a reverse (X6 1, Y12 signal) word code is issued from register 15. Information 33 bits of the register 15 are fed to the first inputs of the correction unit 16 and the second inputs of the adders 17 are modulo two. The control 34 bits of the register 15 are fed to the second inputs of the correction unit 16.

In the absence of errors in the read word, zero signals appear at the first 35 outputs of the correction block, the code word is transmitted unchanged through adders 17 and received at the first 14 output register (by signal Y14). At the same time, at the output of a group of 31 elements OR a zero signal (X5 0). At signal Y17, a code word from register 14 is output to device 40.

If an error of the nth bit is detected by the correction unit 16 at its nth output 35, a single signal arrives at the first input of one of the adders 17, where the error is corrected, the nth bit of the word is transmitted to the first output register (signal Y 14). In addition, at the output of the OR elements 31, a signal X5 1 is generated, which is fed to the fifth input 45 of block 18 and provides the generation of control signals Y3 and Y15. These signals trigger reading the first 19 and second 23 associative drives. In case of absence in argument part 20

and 24 addresses coinciding with the address of the address (X1 0, X2 0), the address with the formative - L 3 is recorded in the free cell of the drive 23, (by signal Y16). Then, the contents of the register 14 is outputted to the output 40 of the device (signal Y17), and the control unit 18 is reset to provide a ready signal (YO) to the output 50 of the device. Thus, upon detection of the first error in the read word, the cell 1 is fixed in the second 23 associative store.

After the read-out word is output to the device output 40, the control unit 18 is initialized, a signal YO of the device ready to execute another command is issued.

In the pauses between a write access and a read to the device,

Operation Control. In this mode, a single potential signal is supplied to the input 49 of the device, which triggers the control unit 18. By signal Y18, the cells of the second 23 associative store are accessed. If all the cells of the drive are free, then the device is reset to the initial state by the alert signal XZ 0. Otherwise, the contents of the argument part 24 of the first occupied cell of the drive 23 are read and transferred through the second 12 switch by signal Y19 to the former 3. In this case, the given cell of the drive 23 becomes unoccupied (the busy bit is reset). Then, the drive 1 is read (Y9) and the code word is received on the second 15 output register (Y10), from where its direct code goes to the inputs of the correction unit 16 and to the second input of the adders 17 modulo two. If on one of the outputs 35 of block 16 there is a single signal (X5 1), then the first 19 associative drive is written

(Y20). The address from the shaper 3 is entered into the argument part 20, the number of the failed discharge from the outputs 36 of the block 16 is entered into the attribute part 21, and the type of failures (0 or 1) s is entered into the functional part 22

a failure type analysis unit. The corrected codeword is received in register 14 (Y14). Next, the code word through the inputs 39 of the first 8 switch enters the inputs of the input 5 register and block 9 encoding

and is written to the drive 1 in the manner described. In this case, the value of the recorded symbol is matched with the type of failure of the inoperative bit,

i.e., the codeword will be written in reverse code.

If, however, a unit did not appear at any of the inputs of the correction unit 16 (X5 0), then the device is reset. In the absence of write and read requests, the next cell is monitored, the address of which is recorded in the second 23 associative drive,

Thus, in the monitoring mode, faults and failures of drive cells 1 are selected and the type of failures of inoperative bits is matched with the value of the recorded characters. This allows, for example, when using a correction code with the correction of single errors, to correct two errors in each word: one error caused by a failure of a bit by means of matching, and the second error caused by a failure or failure of another bit using a correction code, i.e. increase the reliability of the device.

Claims (1)

The claims A memory device with autonomous control, comprising an address storage device, a first associative storage device, an address signal generator, an input register, an encoding unit, a correction unit, modulo two adders, a first output register, first and second switches and a group of OR elements, the outputs of the address signal generator connected to the address inputs of the address drive, the information inputs of which are connected to the outputs of the input register, the information inputs of the first group of the input register are connected to the outputs of the coding unit, the information outputs of the device are the outputs of the first output register, the information inputs of which are connected to the outputs of the adders modulo two, the first inputs of which are connected to the corresponding outputs of the first group of the correction unit, the outputs of the second group of which are connected to the corresponding information inputs of the first associative drive, the control output of which is connected to the first input of the control unit, the outputs of which are connected to the corresponding control inputs of the input first and second output registers, a first correction unit associative accumulator, characterized in that, in order to increase the device reliability, it introduced a second associative storage device, the second output register, the third switch, the control unit, an analysis unit and a comparison unit, the information inputs of the device being the inputs of the first group of the first switch, the inputs of the second group of which connected to the outputs of the first output register, the outputs of the first switch are connected to the corresponding inputs of the encoding unit and the information inputs of the second group of the input register, inputs the address signal driver is connected to the corresponding outputs of the second switch, the inputs of the first group of which are the address inputs of the device, the inputs of the second group of the second the switches are connected to the corresponding address outputs of the second associative drive, the address inputs of which and the address inputs of the first associative drive are combined and connected to the corresponding outputs of the address signal generator, the output of the analysis unit is connected to the information input of the first associative drive, information outputs of the group which is connected to the corresponding inputs of the first group of the third switch, the inputs of the second group of which are connected to the direct outputs of the input register, the output of the third switch is connected to the first input of the comparison unit, the second input of which is connected to the information output of the first associative drive, the first and second control outputs of the second associative drive connected to the second and third inputs of the control unit, the fourth input of which is connected to the output of the comparison unit, the fifth input of the control unit is connected to the output of the group of elements OR, inputs which and. the inputs of the first group of the analysis unit are combined and connected to the corresponding outputs of the first group of the correction unit, the inputs of the first group of which, the inputs of the second group of the analysis unit and the second inputs of the respective adders are modulo two combined and connected to the corresponding outputs of the first group of the second output register, the outputs of the second group which is connected to the inputs of the second group of the correction unit, the output of the second output register is connected to the sixth input of the control unit, the seventh, eighth and ninth inputs of which are the control inputs of the device, the information inputs of the second output register are connected to the corresponding outputs of the address drive, the outputs of the control unit are connected to the corresponding control inputs of the second associative drive, the first, second and third switches, the second output register and the comparison unit, the control inputs of the address drive are connected to the outputs of the control unit, the first output of which is the control output of the device. Block Input Number 18 Signal Symbol 41 42 43 44 45 46 13 inputs through the second 12 switch to the shaper 3 Transmission of the code word from the informational 11 input through the first 8 switch to the input 5 register block 9 Request to the first 19 associative read drive Controlling the operation of the third 26 switch transmitting the symbol of the code word of the input 5 register indicated by the contents of the sign 21 part of the non-power supply 19 Job Management (5lock & 27 comparisons Issuing a reverse code of the contents of the input 5 register to the inputs of the drive 1 Issuance of a direct code of the contents of the input 5 register to the inputs of drive 1 Table Signal conditioning conditions Availability of address in the argument part 20 of the first 19 associative drive The presence of the address of the appeal in the argument part 24 of the second 23 associative drive Second 23 associative drive is empty Matching bit value of recorded word with type of rejection Error in the read word Read Codeword from drive in reverse code Table 2 Y2 3H-Q2 Y3 3n-Q3-C4-Q6V YKHTP-Q9 Y1 Sn-Q tVKHTP Q 10 Y5 3n Q5VKHTp.Q11 Y6 3n-Q6 X2VKHTP-Ql2 Y7 ZP p6 X2 the drive to occupy the cells Y19 Forwarding address from the second associative drive through the switch 12 to the shaper 3 Y20 Request to the first 19 associative drive by record Y21 Forwarding a code word from the output AND register through switch 8 to register 5 and block 9 Continuation of Table 2 Y19 KHTP-Q2 Y20 KHTP-Q7 Y21 KHTP-Q8. figure 4 FIG. 2 yyh.el.Z Figure 5