GB1584537A - Data processing - Google Patents
Data processing Download PDFInfo
- Publication number
- GB1584537A GB1584537A GB18627/78A GB1862778A GB1584537A GB 1584537 A GB1584537 A GB 1584537A GB 18627/78 A GB18627/78 A GB 18627/78A GB 1862778 A GB1862778 A GB 1862778A GB 1584537 A GB1584537 A GB 1584537A
- Authority
- GB
- United Kingdom
- Prior art keywords
- data processing
- store
- micro
- counting
- programme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 title claims abstract description 63
- 230000002441 reversible effect Effects 0.000 claims abstract description 22
- 238000003860 storage Methods 0.000 claims abstract description 14
- 230000000007 visual effect Effects 0.000 claims abstract description 4
- 238000009434 installation Methods 0.000 claims description 39
- 238000012546 transfer Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 210000000352 storage cell Anatomy 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000001419 dependent effect Effects 0.000 claims description 2
- 230000000977 initiatory effect Effects 0.000 claims description 2
- 230000014759 maintenance of location Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 125000004122 cyclic group Chemical group 0.000 abstract description 2
- 230000001960 triggered effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- Debugging And Monitoring (AREA)
Abstract
For the sequential tracing back of completed elementary operations in an error case, an elementary operation memory (EO-M) is provided for temporarily storing a multiplicity of successive microprogram addresses. The storage spaces are addressed by a cyclic up/down counting arrangement (Z1, Z2) which, in the normal operating condition of the DPS, receives counting clock signals (T1) derived from a system clock and, in the error case, counting pulses triggered by a key switch (TS). The memory output lines are connected to one light-emitting diode each of a field for the visual indication of a microprogram address read out. The device simplifies fault finding and enables stored microprogram addresses to be indicated and read in the reverse order of storage. This makes it possible to locate uncorrectable errors in a microprogram-controlled data processing system. <IMAGE>
Description
(54) DATA PROCESSING
(71) We, SIEMENS
AKTIENGESELLSCHAFT, a German
Company, of Berlin and Munich, Federal
Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:
The invention relates to a microprogramme-controlled data processing installation and especially to means for facilitating fault-tracing therein.
Commercial data processing installations are often constructed to be microprogramme-controlled. This means that large parts of the control unit of a data processing installation no longer require to be completely constructed in permanently wired circuit arrangements but are replaced by microprogrammes which are deposited in fixed word stores or recordable stores and which consist of a sequence of microcommands. Each micro-command defines a so-called elementary operation of the data processing installation. i.e. coupled with timing signals derived from a system clock of the data processing installation it establishes specific switching states of the remaining.
simpler hardware of the control unit. Expressed in simple terms. this means that a command can be interpreted at the machine command level of the data processing installation by a micro-programme whose microcommands each establish consecutive switching states of the control unit of the data processing installation in order to be able to consecutively execute the processing steps required for the processing of a machine command.
In a data processing installation of this kind. programmes can run in faulty fashion due to hardware of micro-programme faults.
As a rule a fault which has occurred and been recognised can be relatively easily determined and then corrected. Although many faults can be relatively easily recognised, for example parity faults in a register content, it is not simple to establish all fault origins i.e.
to readily localise all faults which occur.
One possibility of localising faults during a fault handling routine consists, in microprogramme-controlled data processing installations, in backtracking the course of the last elementary operations to have been carried out in the data processing installation. If, as a result of an established fault which cannot be readily corrected in respect of hardware, the control unit of a data processing installation passes from its normal processing state into a fault state, in the event of a programme break which is frequently involved, generally the up-to-date processing state is conserved. All the requisite items of information are safeguarded and intermediately stored so that when the fault has been treated, in the normal state the data processing installation can continue the programme processing without any loss of information.
In micro-programme-controlled data processing installations this generally means that in the fault state, at least one has available the address of the micro-command during the execution of which the fault was established. Frequently even the addresses for the preceding and following micro-commands are intermediately stored in registers which are accessible during the fault handling.
However, this is only a very small section of an executed sequence of micro-commands which finally led to the established fault.
Therefore in many cases these short items of information are not sufficient to localise any possible fault. Therefore in particular in micro-programme-controlled data processing installations under these circumstances fault hunting requires a high time outlay.
This is due to the fact that frequently microprogrammes also contain programme jumps and programme loops and these nonlineanties must be taken into account in backtracking a micro-programme.
Therefore the aim of the invention is to provide a device in which this backtracking of elementary operations which have been executed prior to an established fault can be carried out in a simple manner.
According to the present invention, there is provided a micro- programme-controlled data processing system having a control unit and at least one microprogramme store, and including a reversible cyclically operable sequential-access auxiliary store means arranged, in fault-free operation of the system, to operate in a first direction, means arranged, in fault-free operation of the system, to continually write into successive locations of the auxiliary store means the address of each micro-programme store location accessed by the control unit, means responsive to a fault condition in said system to reverse the direction of operation of the auxiliary store means, and means operable in said fault condition to read from the auxiliary store means whereby the addresses of the preceding micro-programme instructions accessed are available to the user in sequential form in the reverse sequence to that in which they were stored.
Preferably, to facilitate the backtracking referred to above, the micro-programme addresses of a large sequence of microcommands can be readily reproduced even following the occurrence of a fault. This realisation has the advantage of using simple circuitry means which can allow the addresses of a large number of the last microcommands to have been executed to be stored in dynamic operation and to be read out in the reverse sequence of their storage in the stop state or fault state of the data processing installation.
The auxiliary store means preferably comprises a random access memory which is referred to as elementary operations store and the storage positions of which each permit the storage of a complete microprogramme address. This memory is then addressed with the aid of the output signals of a cyclically operable reversible counter which may be clocked in either counting direction. Thus, during the normal operation of the data processing installation, the counter counts each elementary operation, and an address signal for the elementary operations store is derived from the count and the micro-programme address of the current elementary operation is recorded in the storage position which has been established in this way.
In the stop state or fault state of the data processing installation, the forwardsbackwards counting arrangement is automatically set at (say) the "backwards" counting direction. In this state the elementary operations store can be addressed by counting pulses, which for example can be produced manually, in such manner that the stored micro-programme addresses can be read out sequentially therefrom in the reverse sequence to which they were input. In view of the current prior art there are no difficulties .involved in constructing an elementary operations store of this kind with a capacity of for example 128 micro-programme addresses and when large scale integrated circuits are used this means only a relatively small store.
The forwards-backwards counting arrangement which can be constructed from commercially available modules and which serves to address this store allows a store of this kind to be dynamically addressed and cyclically operated using simple means. The address signals can be obtained from timing signals which are in any case required to control the flow of an elementary operation in the control unit of conventional data processing installations so that neither do any systematic difficulties occur in integrating the auxiliary store and associated control means into a micro-programme-controlled data processing installation without extensive modifications. This is a useful preferred feature of the invention as it allows the provision of a simple auxiliary means which can considerably simplify servicing or diagnostic work.
In preferred embodiment, the system includes display means for visual display of the address information read from the auxiliary store means. The display means may for example comprise a plurality of lightemitting diodes connected via a buffer to the data read-out lines of the auxiliary store.
An exemplary embodiment of the invention will now be described with reference to the accompanying drawing which is a diagram of one form of data processing system according to the invention.
Micro-programmes which determine the operating flow of a control unit, not illustrated in its entirety, of the data processing installation can be deposited in a recordable control store WCM which for example also forms a part of the main store of the data processing installation non-accessible to machine programmes, and/or in a fixed word store ROM. The register contents of a micro-programme address register MPAR represent the complete address for a microcommand, which defines a following elementary operation, of à micro-programme. The register contents can be divided into two parts, one section for a micro-command address ADR and a store selection section
SA whose bit configuration defines the addressable micro-programme store WCM or ROM from which this micro-command is to be selected at the addressed storage position. As indicated in the drawing, the bit configuration of the store selection section
SA is analysed in a selection control unit SAS
whose output signals, via schematically indi
cated switching elements, permit the addres
sing of the selected micro-programme store
WCM or ROM with the micro-command
address ADR. The further processing of a
read-out micro-command within the control
unit of the data processing installation has
not been represented as it is of no signifi
cance in the present context.
A longer sequence of micro-programme
addresses of this kind which each relate to an
elementary operation of the control unit of
the data processing installation is now to be
intermediately stored in such manner that it
is available over a longer period of time.
Thus, in the event of the appearance of a
fault, these addresses are to' be used to
determine the events which led up to this
fault. For this purpose an elementary opera
tions store EO-M is provided which for
example posses 128 storage positions each
for one micro-programme address. If a com
plete micro-programme address comprises
16 bits, as has been assumed in this exemp
lary embodiment a store consisting of 16
storage modules constructed in semiconduc :tor technology each having 128 storage cells
each for one bit can be constructed as
schematically indicated in the drawing.
Input-end data write-in lines I to I15 of this
elementary operations store EO-M are con
nected to the outputs of the micro
programme address register MPAR, and
output-end data read-out lines 0 to 015 are
each connected via a multiple AND-gate
UG1 for mutual decoupling and via a termi
nal resistor R1 to negative operating voltage
UB. Each of these output lines is connected
to a light-emitting diode LED which is con
nected from the junction of the AND-gate
UG1 and the terminal resistor R1 to earth.
The light-emitting diodes can either be arranged in a display section of a test device for servicing purposes or a servicing section
of the data processing installation itself.
Then the address bit positions of a binarycoded micro-programme address can be read
out from the display pattern of the light
emitting diodes LED.
This elementary operations store EO-M is
now to be operated in such manner that in
the normal state of the data processing instal
lation, i.e. for such time as it operates free of
faults, it always contains the sequence of the
128 micro-programme addresses which were
the last to have been accessed. Therefore for
the addressing of this store there is provided
a cyclically counting forwards-backwards
counting arrangement which is constructed
from two series-connected four-position
up-down counters Z1 and Z2. These com
mercially available counter modules can
each be set to the up or down counting direc
tion by a control signal at one of its inputs U and D. A further input T of the forwardsbackwards-counter Z1 and Z2 forms the input for the counting pulse. The figure further indicates that the modules are connected to one another by control lines CB for carry- and borrow-signals.
The two up-down-counters Z1 and Z2 are connected in such manner that together they are able to count from PJ to 127, and the highest stage of the second forwardsbackwards-counter Z2 is not used. Accordingly the four output lines of the first updown counter Z1, together with three lowvalue output lines of the second up-down counter Z2, are connected to seven address inputs A to A6 of the elementary operations store EO-M. Thus, in cyclic progression, one of the 128 storage positions of the elementary operations store EO-M can be selected for a micro-programme address by the output signals of the forwards-backwards counting device.
For completeness it will be mentioned that the elementary operations store naturally also possesses the conventional module selector inputs which have not been shown here. In fact in each selection process of the store, each storage module is selected and consequently these selector inputs are statically supplied with a signal, i.e. in permanently wired fashion.
The forwards-backwards counting device
Z1, Z2 is assigned an input circuit which supplies control signals for "forwards" and "backwards" setting of the counting direction, and likewise the counting pulses. During the normal state, i.e. during fault-free operation, an operations signal OS is produced in the control unit of the data processing installation. This signal (which is usually available in conventional systems) is employed to form the control signals for the counting direction. For this purpose the operations signal OS is supplied to one input of a second AND-gate UG2 whose second input is permanently wired to logic 1. It possesses two outputs which are inverted to one another and which are connected to the two counter inputs U and D for the "forwards" and "backwards" counting directions of the two up-down counters Z1 and Z2. In the normal operation of the data processing installation the "forwards" counting direction is set automatically. In the fault state of the data processing installation the operations signal OS does not occur in which case the two up-down counters Z1 and Z2 are automatically set at the "backwards" counting direction.
The operations signal OS is also conducted to one of the two inputs of a further ANDgate UG3 whose second input is connected to a transfer timing signal T2 derived from a system clock of the control unit of the data processing installation. This signal, which is
conventionally produced in the control unit
of a data processing installation, and which -serves to initiate the execution of an elemen
tary operation by reading out the associated
micro-command from one of the selected
micro-programme stores WCM or ROM, is
used here to initiate a write operation in the
elementary operations store EO-M. There
fore the output of this further AND-gate
UG3 is connected to -a write control input
WE of the elementary operations store. At
the time of the occurrence of this transfer
timing signal T2, the micro-programme
address contained in the micro-programme
address register MPAR is "fixed" and is then
transferred into the particular selected stor
age position of the elementary operations
store EO-M.
To allow the two up-down counters Z1 and
Z2 to count onwards and thus to form the
next address for the elementary operations
store EO-M, the output of a OR-gate OG is
connected to clock inputs T of both up-down
counters Z1 and Z2. One of the two inputs of
this OR-gate OG is connected to a counting
timing signal T 1 likewise derived from the
system clock of the data processing-installa- tion. This counting timing signal is provided
for other purposes of the control unit of the
data processing installation and for example
is logic-linked with the initiation of the pro
duction of a new micro-command. Therefore
it only occurs for such time as the control unit
of the data processing installation is operat
ing in the normal state, i.e. in fault-free oper
ation. Therefore the counting device is step
ped on by the counting timing signals T1 only
in the "forwards" counting direction.
In the event of a fault, as explained, the
forwards-backwards counting device is
automatically set to the "backwards" counting direction as a result of the cessation of the
operations signal OS. In this state the count
ing pulses are produced by a circuit arrange
ment which is connected to the second input
of the OR-gate OG. This circuit arrangement
consists of a keying switch TS which on one
side is connected to earth and whose second
contact is connected via a resistor R2 to a circuit node which is connected via a
capacitor C on the one hand to earth and via
a further resistor R3 to a negative potential --UB. This network forms a de-bounce circuit
for the switching pulses of the keying switch TS. The circuit node of this network is con
nected to a signal input of a receiving amp lifer EV whose feedback arm contains a
coupling resistor R4. This receiving amplifier
converts the keying signals which have been emitted from the keying switch TS and have
been relieved of chatter and matches these to
the level conditions otherwise prevailing in
the circuit. The converted keying signals are fed from the output of the receiving amplifier
EV to the second input of the OR-gate OG and thus represent the relevant counting pulses for the forwards-backwards counting device in the "backwards" counting direction.
Thus this circuit arrangement permits micro-programme addresses intermediately stored in the elementary operations store
EO-M to be addressed in the reverse sequence in which they were stored. On account of the absence of the operations signal OS, the write-in control input WE of the elementary operations store EO-M is not operated in this state. Thus only a read-out process is possible. The contents of a storage cell, addressed in this way, within this store is read out via the data read-out lines 0 to 015 and displayed in the output section by the lightemitting diodes LED.
WHAT WE CLAIM IS:
1. A micro-programme-controlled data processing system having a control unit and at least one micro-programme store, and including a reversible cyclically operable sequential-access auxiliary store means arranged, in fault-free operation of the system, to operate in a first direction, means arranged, in fault-free operation of the system, to continually write into successive locations of the auxiliary store means the address of each micro-programme store location accessed by the control unit, means responsive to a fault condition in said system to reverse the direction of operation of the auxiliary store means, and means operable in said fault condition to read from the auxiliary store means whereby the addresses of the preceding micro-programme instructions accessed are available to the user in sequential form in the reverse sequence to that in which they were stored.
2. A data processing system as claimed in claim 1, in which the auxiliary store means comprises a random-access memory and a cyclically operable reversible counter the output of which is operatively connected to the address input of the memory.
3. A data processing system as claimed in claim 1 or 2, in which the means operable to read from the auxiliary store means includes switching means operable by the user to produce pulses for stepping the counter in said reverse direction and reading from the store.
4. A data processing system as claimed in claim 1, 2 or 3, including display means arranged for visual display of the address information read from the auxiliary store means.
5. A data processing system as claimed in claim 4, in which the display means comprises a plurality of light-emitting diodes connected via a buffer to the data read-out lines of the auxiliary store means.
6. A data processing system as claimed in claim 3 when dependent on claim 2, in which the reversible counter consists of two series
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (9)
1. A micro-programme-controlled data processing system having a control unit and at least one micro-programme store, and including a reversible cyclically operable sequential-access auxiliary store means arranged, in fault-free operation of the system, to operate in a first direction, means arranged, in fault-free operation of the system, to continually write into successive locations of the auxiliary store means the address of each micro-programme store location accessed by the control unit, means responsive to a fault condition in said system to reverse the direction of operation of the auxiliary store means, and means operable in said fault condition to read from the auxiliary store means whereby the addresses of the preceding micro-programme instructions accessed are available to the user in sequential form in the reverse sequence to that in which they were stored.
2. A data processing system as claimed in claim 1, in which the auxiliary store means comprises a random-access memory and a cyclically operable reversible counter the output of which is operatively connected to the address input of the memory.
3. A data processing system as claimed in claim 1 or 2, in which the means operable to read from the auxiliary store means includes switching means operable by the user to produce pulses for stepping the counter in said reverse direction and reading from the store.
4. A data processing system as claimed in claim 1, 2 or 3, including display means arranged for visual display of the address information read from the auxiliary store means.
5. A data processing system as claimed in claim 4, in which the display means comprises a plurality of light-emitting diodes connected via a buffer to the data read-out lines of the auxiliary store means.
6. A data processing system as claimed in claim 3 when dependent on claim 2, in which the reversible counter consists of two series
connected, four-stage binary up-down counter devices, and further including an
OR-gate whose output is connected to the count-pulse inputs of the counter devices, whose first input is supplied, in the normal operating state, with counting pulses derived from a system clock of the system and whose second input is connected to receive said reverse counting. pulses from the switching means, an AND-gate with normal and inverted outputs connected to up and down control inputs for "forwards" and "backwards" counting directions of the counter devices and whose one input is connected to receive an operations signal which is actuated only in said normal operating state, and a further AND-gate whose inputs are supplied with the operations signal and with a further transfer timing signal derived from the system clock of the data processing installation and whose output is connected to a write-in control input of the auxiliary store means which, in the activated state, triggers a transfer of the micro-programme address offered on the data write-in lines into the addressed storage position of the auxiliary store means.
7. A data processing system as claimed in claim 6, in which, for the production of backwards counting pulses in the fault state of the data processing installation, the switching means comprises a keying switch whose input contact is connected to earth and whose output contact is connected via a de-bounce circuit and via a receiving amplifier for level conversion to the OR-gate.
8. A data processing system as claimed in claim 7, in which the de-bounce circuit arranged between the keying switch and the receiving amplifier consists of a series resistor which is connected to the output contact of the keying switch and whose other terminal is connected via a capacitor to earth and via a further resistor to a negative operating potential.
9. A data processing system substantially as herein described with reference to the accompanying drawing. ,, -
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2737350A DE2737350C2 (en) | 1977-08-18 | 1977-08-18 | Device for error handling in a microprogram-controlled data processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1584537A true GB1584537A (en) | 1981-02-11 |
Family
ID=6016761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB18627/78A Expired GB1584537A (en) | 1977-08-18 | 1978-05-10 | Data processing |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5443436A (en) |
| BE (1) | BE869852A (en) |
| CH (1) | CH625067A5 (en) |
| DE (1) | DE2737350C2 (en) |
| FR (1) | FR2400731A1 (en) |
| GB (1) | GB1584537A (en) |
| IT (1) | IT1097648B (en) |
| NL (1) | NL7806903A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2275119A (en) * | 1993-02-03 | 1994-08-17 | Motorola Inc | A cached processor. |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4315313A (en) * | 1979-12-27 | 1982-02-09 | Ncr Corporation | Diagnostic circuitry in a data processor |
| DE3038143C2 (en) * | 1980-10-09 | 1983-12-29 | Brown, Boveri & Cie Ag, 6800 Mannheim | Arrangement for troubleshooting a programmable controller |
| JPS631723U (en) * | 1986-06-21 | 1988-01-07 | ||
| CH672552A5 (en) * | 1987-08-20 | 1989-11-30 | Jean Claude Mermod |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2258668A1 (en) * | 1974-01-18 | 1975-08-18 | Labo Cent Telecommunicat | Data processor tracing unit - permits real time monitoring of system operation especially in telephone exchange systems |
| US4016543A (en) * | 1975-02-10 | 1977-04-05 | Formation, Inc. | Processor address recall system |
-
1977
- 1977-08-18 DE DE2737350A patent/DE2737350C2/en not_active Expired
- 1977-12-20 CH CH1564177A patent/CH625067A5/en not_active IP Right Cessation
-
1978
- 1978-05-10 GB GB18627/78A patent/GB1584537A/en not_active Expired
- 1978-06-27 NL NL7806903A patent/NL7806903A/en not_active Application Discontinuation
- 1978-08-08 FR FR7823355A patent/FR2400731A1/en not_active Withdrawn
- 1978-08-11 IT IT26704/78A patent/IT1097648B/en active
- 1978-08-18 BE BE189974A patent/BE869852A/en unknown
- 1978-08-18 JP JP10083578A patent/JPS5443436A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2275119A (en) * | 1993-02-03 | 1994-08-17 | Motorola Inc | A cached processor. |
| US5586279A (en) * | 1993-02-03 | 1996-12-17 | Motorola Inc. | Data processing system and method for testing a data processor having a cache memory |
| GB2275119B (en) * | 1993-02-03 | 1997-05-14 | Motorola Inc | A cached processor |
Also Published As
| Publication number | Publication date |
|---|---|
| IT1097648B (en) | 1985-08-31 |
| DE2737350C2 (en) | 1979-08-23 |
| BE869852A (en) | 1979-02-19 |
| DE2737350B1 (en) | 1978-12-14 |
| IT7826704A0 (en) | 1978-08-11 |
| CH625067A5 (en) | 1981-08-31 |
| JPS5443436A (en) | 1979-04-06 |
| NL7806903A (en) | 1979-02-20 |
| FR2400731A1 (en) | 1979-03-16 |
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| PCNP | Patent ceased through non-payment of renewal fee |