JPS61182151A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory containing a test mode for functions of an ECC (error detection/correction) circuit system by using virtual data for the ECC circuit system. CONSTITUTION:A write check bit latch circuit is provided to store temporarily the write check bit together with a check bit switching circuit 12 which switches the data supplied to a syndrome generating circuit 5 according to a control signal TE and an input switch circuit 10 which switches the data supplied to a read check bit generating circuit 4 according to the signal TE. Thus the virtual data can be used for an ECC circuit system and therefore an independent test is possible with functions of the ECC circuit system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having an error detection and correction (hereinafter referred to as rEccj) function.

[Conventional technology]

In recent years, as semiconductor memory devices have become more highly integrated, malfunctions of memory cells due to incidence of α particles, ie, soft errors, have become a problem. As a countermeasure to this problem, on-chip ECC is being implemented in which the ECC function is provided on the same semiconductor substrate.

FIG. 4 shows a circuit example of a conventional on-chip ECC semiconductor memory device. In Figure 4, 1 is an input terminal to which data bit a is input, and 2 is a write terminal from data bit a.
A write check bit generation circuit 3 generates check bit b; 3 is a memory cell array 3a that manually stores data bit a and write check bit b and outputs it as necessary; 3b is a data bit array that inputs data bit a and outputs new data bit C, and 3b is a check bit array that inputs write check bit b and outputs new write check bit d. , 4 is a read check bit generation circuit that inputs data bit C and outputs a new check bit e, 5 is a syndrome generation circuit that has an exclusive OR function and outputs syndrome f, and 6 is a syndrome A syndrome decoder decodes f and outputs syndrome decode data g, and 7 a data correction circuit that corrects data bit C and write check bit d using syndrome decode data g and outputs corrected data h and external output data i. , 8 is an address decoder for selecting external output data j to be output to the outside, and 9 is an output terminal for outputting external output data J.

Next, the operation of the device configured as described above will be explained. When writing data bit a of m0 bits input to input terminal 1, write check bit generation circuit 2 generates a check for data bits of multiple bits (referred to as m bits) including data bit a. A write check bit (k bits) b is generated, and the write check bit b and m data bits are written into the memory cell array 3.

When reading data from memory cell array 3, bit write/check is performed on m-bit data bit C and
Bit d is read at the same time, and the read check bit generation circuit 4 generates a read check bit from this m-bit data bit C as a new check bit.
Generate bit e. Next, the syndrome generating circuit 5 checks this read check bit e and the memory cell.
Write check bit d read from array 3
Perform bitwise exclusive OR with . As a result, if all bits are "0", it is determined that there is no error; otherwise, it is determined that there is an error. The fact that all pinot hs are "0" means that the read check bit e and the write check bit
This means that bit d matches. The data of the exclusive OR described above is called a syndrome. A syndrome is a data string consisting of bits. Syndrome generation circuit 5 outputs syndrome r to syndrome decoder 6.

The syndrome f described above includes position information of error bits, and by decoding this with the syndrome decoder 6, it can be determined which bit is an error. Accordingly, in the data correction circuit 7, the m-bit data bit C and the bit write check are performed.
Correct, ie, invert, the incorrect bit d. Generally, among the m-bit corrected data group, m is the external data output. It's a bit. In this case, m0
≦m bits. Therefore, external output data j output from address decoder 8 is selected and output according to address information k input to address decoder 8. In many cases, the address decoder 8 can also serve as an access decoder (not shown).

Write check bit generation circuit 2. The read check bit generation circuit 4 is a circuit that generates check bits from m-bit data bits according to the configuration of the error detection/correction code, and since the logic operations are the same for both, the same circuit can be used for both. There is also a method. Furthermore, as described above, the syndrome generation circuit 5 receives the write check bit d read from the memory cell array 3 and the read check bit newly generated from the data bit C in the read check bit generation circuit 4. check pick l-
This is a circuit that performs a bit-wise exclusive OR with e. The syndrome decoder 6 converts the k-bit syndrome f into m
It is a decoder that converts the error bit of the data bit C of the bit and the write check bit d of the bit into the code of the m+ bit, for example, m
+ Obtain an output in which only the error bit position among the k bits is "1" and the others are "0". The data correction circuit 7 is a circuit that performs a bit-by-bit exclusive OR of the syndrome decoded data g output from the syndrome decoder 6, the data bit C to be corrected, and the write check bit d. , the data of only the error bit is inverted, that is, the error is corrected. The m+k bits of corrected data h whose errors have been corrected are written again to a predetermined position in the memory cell array 3. moreover,
Among the corrected m-bit data bits i, the accessed m0 data bits are selected by the address decoder 8 and become external output data j.

Next, a functional test of a conventional semiconductor memory device will be explained. The main functional tests are (al data bit array 3a (b) check bit array 3b (C) E CC circuit system. (al can be realized by stopping the ECC function. , (b) can be realized by making the check bit array 3b directly accessible from the outside.However, there is no effective means for (C).

[Problem that the invention seeks to solve]

Since the conventional semiconductor memory device with on-chip ECC is configured as described above, there is a problem in that it is not possible to perform a functional test of only the ECC circuit system.

The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor memory device equipped with a test mode in which the function of an ECC circuit system can be tested.

[Means for solving problems]

In order to solve these problems, the present invention has developed a light
A write check bit latch circuit for temporarily storing check bits, a first switching means for switching data input to the syndrome generation circuit according to a control signal, and input to the read check bit generation circuit. A second switching means for switching data according to a control signal is provided.

[Effect]

In the present invention, a functional test of the ECC circuit system is performed using virtual data output from the second switching means.

〔Example〕

An embodiment of a semiconductor memory device according to the present invention is shown in FIG. In FIG. 1, 10 is an input switching circuit as a second switching means that switches the data input to the read check bit generation circuit 4 using a control signal, and 1) temporarily stores the write check bit. A write check bit latch circuit 12 is a check bit switching circuit as a first switching means for switching data input to the syndrome generating circuit 5 by a control signal. In FIG. 1, the same or equivalent parts as in FIG. 4 are given the same reference numerals. In terms of configuration, this device differs from the conventional semiconductor memory device shown in FIG.
) and a check bit switching circuit 12.

The functions of these three circuits will be explained. First, the input switching circuit 10 will be explained. This circuit uses the control signal TE
The following operations are performed according to the following. In normal mode, that is, in TE-rLJ, read/check/
The data, bit c, output from the data bit array 3a is input to the bit generating circuit 4, and a normal Ecc operation is performed. In test mode, i.e. TE= rHJ
When O, to read check bit generation circuit 4.

Certain fixed data, for example, data in which all bits are "O" (hereinafter abbreviated as "all bits = OJ")
Enter. Thereby, in the test mode, certain virtual data, for example, all bits=0, can be input to the read check bit generation circuit 4 regardless of whether the data bit array 3a is good or bad. A concrete example of this circuit is shown in FIG. In Figure 2, A1
-Am is an input terminal to which m-bit data bits C are input, and 20 is an input terminal to which a control signal TE is input.

Next, the write check bit latch circuit 1) will be explained. This circuit is a latch circuit that temporarily stores a write check bit generated during a write operation. This content is rewritten every time a write operation is performed.

Next, the check bit switching circuit 12 will be explained.

This circuit operates as follows in accordance with the control signal TE. In normal mode, that is, TE=rL
When J, write check bit d from check bit array 3b is input and normal ECC operation is performed. In the test mode, that is, when TE=rHj, data from the write check bit latch circuit 1), that is, the write check bit generated during the previous write operation, is input to the syndrome generation circuit 5. A concrete example of this circuit is shown in FIG.

In FIG. 3, B is an input terminal to which the write check bit of the bit is input, and 30 is an input terminal to which the control signal TE is input.

E of a device composed of a circuit having such a function
The operation of the CC test mode will be explained below. Data bit array 3a, check bit
It is assumed that the operation of array 3b has been completed, that is, it has been confirmed that all memory cell arrays 3 are good. Read/check/in test mode
When data with all bits=O is input to the bit generation circuit 4, a read check bit e is generated for this virtual data. Therefore, during the previous write operation, all data bits in the same ECC circuit system were set to 0.
If the ECC circuit system is operating normally, data correction will not be performed on any of the target data bits, and all correction data h will be "0". . If you wrote data with only a certain bit as "1" and the others as "0" during the previous write, "
Data correction should be performed on the bit position where "1" is written, and if the corrected data h is all "0", the ECC circuit system is operating normally. By using virtual data in this way, ECC
Functional tests of circuit systems can be easily performed.

In this embodiment, the virtual data is fixed data in which all bits are 0, but it may be fixed data in which all bits are not zero, or it may be variable data provided from the outside.

Further, although the case of ECC using a Hamming code as an error correction code is shown, it is also applicable to the case of ECC using other methods such as horizontal, vertical, parity check methods, etc.

〔Effect of the invention〕

As explained above, the present invention includes a write check bit latch circuit for temporarily storing a write check bit, and a first switching means for switching data input to a syndrome generation circuit according to a control signal. By providing a second switching means that switches the data input to the read/check/focus generation circuit according to the control signal, virtual data can be used in the ECC circuit system, so the functions of the ECC circuit system can be operated independently. This has the advantage that it is possible to easily perform a functional test of a semiconductor memory device with on-chip ECC.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a detailed circuit diagram of an input switching circuit that constitutes this device, and FIG. 3 is a check bit switching circuit that constitutes this device. Detailed circuit diagram of the circuit. FIG. 4 is a circuit diagram showing a conventional semiconductor memory device. l...Input terminal, 2...Write check bit generation circuit, 3...Memory cell array, 3a...
...Data bit array, 3b...Check bit array, 4...Read check bit generation circuit, 5...Syndrome generation circuit, 6...
... syndrome decoder, 7 ... data correction circuit, 8 ... address decoder, 9 ... output terminal,
10...Input switching circuit, 1)...Write check bit latch circuit, 12...Check bit switching circuit. 25th Ward 3

Claims (3)

[Claims] (1) In a semiconductor memory device that is equipped with a write check bit generation circuit, a read check bit generation circuit, and a syndrome generation circuit for error detection and correction functions on the same board, the write check bit is temporarily a write check bit latch circuit for storing data; and a first circuit that outputs either a check bit array output or an output of the write check bit latch circuit to the syndrome generating circuit according to a control signal.
1. A semiconductor memory device comprising: switching means; and second switching means for outputting either a data bit array output or virtual data to a read check bit generation circuit in accordance with a control signal. (2) The semiconductor storage device according to claim 1, wherein the second switching means changes the fixed data to virtual data. (3) The second switching means is characterized in that the data input from the outside is virtual data.
The semiconductor storage device described in 1.