JPS61278100A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS61278100A
JPS61278100A JP60119130A JP11913085A JPS61278100A JP S61278100 A JPS61278100 A JP S61278100A JP 60119130 A JP60119130 A JP 60119130A JP 11913085 A JP11913085 A JP 11913085A JP S61278100 A JPS61278100 A JP S61278100A
Authority
JP
Japan
Prior art keywords
data
bit
bits
syndrome
check bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60119130A
Other languages
Japanese (ja)
Inventor
Hideto Hidaka
Kazuyasu Fujishima
Masaki Kumanotani
Hideji Miyatake
Katsumi Dousaka
Tsutomu Yoshihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60119130A priority Critical patent/JPS61278100A/en
Publication of JPS61278100A publication Critical patent/JPS61278100A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the time of a write cycle from becoming long, by constituting one error detecting/correcting word by the memory cell data of one group which is brought to an access simultaneously, and a redundant bit data generated from said data.
CONSTITUTION: A write check bit generating circuit 1 and a read check bit generating circuit 5 generate a check bit from a data bit of (m) bits, and a syndrome generating circuit 6 takes an exclusive OR syndrome of every bit, of a write check bit which has been read out of a memory cell 2, and a read check bit which has been generated newly from the data bit. A syndrome decoder 7 converts an error bit in the data bit of (m) bits and the check bit of (k) bits, to a designated code, from a syndrome of (k) bits, and outputs it by a data correcting circuit 8 and an address decoder 9. A data of (m) bits, which is brought to an access simultaneously by forming a data output by (m) bits, and a redundant bit data generated from said data constitute one error detecting/correcting word.
COPYRIGHT: (C)1986,JPO&Japio
JP60119130A 1985-05-31 1985-05-31 Semiconductor memory device Pending JPS61278100A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60119130A JPS61278100A (en) 1985-05-31 1985-05-31 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60119130A JPS61278100A (en) 1985-05-31 1985-05-31 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS61278100A true JPS61278100A (en) 1986-12-08

Family

ID=14753680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60119130A Pending JPS61278100A (en) 1985-05-31 1985-05-31 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS61278100A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0689595A (en) * 1990-02-13 1994-03-29 Internatl Business Mach Corp <Ibm> Dynamic random access memory having on-chip ecc and optimized bit and redundancy constitution of word
US8046665B2 (en) 2006-12-29 2011-10-25 Samsung Electronics Co., Ltd. Memory device employing dual clocking for generating systematic code and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0689595A (en) * 1990-02-13 1994-03-29 Internatl Business Mach Corp <Ibm> Dynamic random access memory having on-chip ecc and optimized bit and redundancy constitution of word
US8046665B2 (en) 2006-12-29 2011-10-25 Samsung Electronics Co., Ltd. Memory device employing dual clocking for generating systematic code and method thereof

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