JPS60167051A - Storage device - Google Patents

Abstract

PURPOSE:To use more data as readout data by writing the same data as data of all blocks during writing operation, reading data, block by block, individually during reading operation, and comparing data of plural blocks, bit by bit. CONSTITUTION:A low-order address 105 is inputted to memory blocks 101-103 to address of a memory cell. A high-order address, on the other hand, is inputted to a decoder circuit 107. A decoder circuit 107 inputs signals from a mode selection switch 109 and a memory area specifying switch 108 and outputs selection signals CS0-CS2 for the respective blocks according to a truth table. The memory blocks selected with the CS0-CS2 are written and read. Two blocks are written and read at the same time in mode I and data are compared during the reading to detect a memory readout error. Further, three blocks are written and read at the same time in mode II and a majority decision on read data is made to secure data against an error of one memory block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a storage device, and particularly to a storage device suitable for easily obtaining high reliability using an IC memory having a word structure of multiple bits.

[Background of the invention]

Traditionally, main memory devices used in computers use parity checks to detect 1-bit errors in order to improve reliability.
Alternatively, methods such as 1-bit error correction and 2-bit error detection using ECC codes are used. Furthermore, depending on the grade and purpose of the equipment used, there are some that are not checked at all. However, for IC memories with a multi-bit word structure, one IC memory supports multiple pinpoints in a data word, so multiple bits can be erroneous at the same time (i.e., one IC memory's basic There is a failure mode in which the output data of that IC is unreliable.

Therefore, there is a defect that parity and ECC cannot achieve sufficient effects. In addition, when a highly integrated mask ROM is used as a memory and redundant configurations such as parity and ECC are adopted, parity data is added in addition to the original content data section of the memory.

It is necessary to create a separate mask containing the ECC information (redundant part), which increases the cost of mask development, and when the data part is changed, the redundant part must also be changed.
The drawback is that at least two mask changes will occur. Also, as IC memory becomes more highly integrated,
A phenomenon may occur in which there are more circuits to implement complex logic such as ECC than actual memory elements, so even if the number of memory elements increases slightly from the perspective of the entire storage device, it is not possible to use a simple redundant circuit. A situation has arisen in which the total number of elements or the cost can be reduced by doing so.

[Purpose of the invention]

An object of the present invention is to provide a storage device that can ensure reliability of memory.

[Summary of the invention]

The present invention provides a storage device in which one or more IC memories each having a word structure of multiple bits are used to form one word, in which a plurality of blocks having the same address are provided, and when data is written, the data in all blocks is the same. The reliability of the memory is improved by writing the data of the address, reading the data individually for each block, comparing the data of multiple blocks for each bit, and determining the larger data as the read data of the address. The aim is to ensure sexuality.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 1 shows an embodiment of the invention.

In the figure, a memory block 10 of n bits x m words is shown.
1, 102, and 103 are configured so that a lower address (address within the memory block) 105 is input. This lower address 105 is divided from the address bus 104, and this address bus 104 is inputted to the decoder circuit 107 by dividing the upper address 106. This lower address 105 is the memory block 10
1°102 and 103 to designate the address of the memory cell. Lower addresses are memory blocks 101-1
03 to designate the address of the memory cell. The upper address is input to the decoder circuit 107. The decoder circuit 107 inputs the signals of the mode selection switch 109 and the memory area designation switch 108, and according to the truth table shown in FIG.
10) Output C8I (111) C82 (112).

In other words, in mode O, the address is the same as the area designation switch (when ω, C8O is used, and the address with one more address (
By separately outputting C81 when the address is (n+1) and 082 when the address is two more (n+2), a memory area for three blocks can be secured. Also,
When in mode I, It (Fig. 2 A5, A7)
is 080. when the address is the same as the contents of the area designation switch. Cal.

C82 (C82 is only in mode ■) is output at the same time. Further, reference numeral 113 shown in FIG. 1 is a write data buffer, which is inserted for the purpose of separating the external data path line 114 into data bus lines 115°, 116, and 117 of each memory block. Write data is C8O
-Written to the memory block selected by C83.

When a plurality of C80 to C83 are selected at the same time, the same data is written to a plurality of blocks at the same time.

Reference numeral 118 in FIG. 1 denotes a read data buffer which outputs read data to the data bus 114 according to a truth table for each bit as shown in FIG. That is, in mode O (modes 0, 0, 1 to 6 in FIG. 3), the read data of the memory block determined by the decoded 08 manual input is output to the data bus 114. When in mode ■ (
Figure 3 Mode 0. The contents of memory block 101 are output to A7 to A10) of memory block 101 at the same time.
The contents of the read data of the memory block 102 are compared bit by bit, and if the contents differ, error information is output. Also, when in mode ■ (A11 to 1 in modes 1 and 0 in Figure 3)
8) includes three memory blocks 101, 102, 103.
Compares the contents of two read data bit by bit and outputs the larger value. If any one item is different, error information is also output. As a result, in mode I, 2
Memory reading errors can be detected by writing and reading blocks and comparing data during reading. In addition, in mode (2), by writing and reading three blocks at the same time and determining the read data by majority vote, data can be guaranteed against an error in one memory block. Furthermore, in mode I, it is possible to guarantee an error detection rate that exceeds parity errors, and in mode -2, it is possible to correct and detect errors that exceed ECC'.

Furthermore, in mode 0, it can be used as main memory with three times the capacity. Furthermore, in mode I, mounting of the memory block 103 is unnecessary.

Woman, decoder 107. The read data buffer 118 is a high-speed ROM*PAL (Programmab
It can be easily made by using a gate array, etc., and is a simpler circuit than an ECC circuit.

In this embodiment, the case where the number of memory blocks is 3 has been explained, but the number of memory blocks can be 6, and in this case, by switching the mode, j) 6×1 memory without error check, 3×2 memory Comparison error detection, 2×
There are three types of majority voting system (3), and there is an effect that unused (unimplemented) blocks do not occur in mode 1 as in the previous embodiment. Decoder 107. Although the read data buffer 118 is somewhat more complicated, it can be realized using the same concept.

Therefore, according to this embodiment, it is possible to provide a hierarchical memory series from highly reliable to popular types using one type of memory package, so that it is possible to provide a series of hierarchical memories from highly reliable types to popular types. An optimal memory configuration can be achieved.

[Knowing the invention]

As described above, according to the present invention, reliability of memory can be ensured.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a truth table of a decoder circuit, and FIG. 3 is a diagram showing a truth table for each bit of a read buffer circuit. 101.102,103...Memory block, 104
... Address bus, 107... Decoder. Bracket 10 20th A---77th child Ia

Claims (1)

[Claims] 1. In a storage device that forms one word by arranging one or more IC memories with a multi-focus word structure,
Create multiple blocks with the same address, write the same data to all blocks when writing, read data individually from each block when reading, and compare the data of multiple blocks for each bit. 1. A storage device characterized in that data on one side is determined to be read data at the address.