PL3308469T3 - Sposoby dopasowywania szybkości dla kodów LDPC - Google Patents

Sposoby dopasowywania szybkości dla kodów LDPC

Info

Publication number
PL3308469T3
PL3308469T3 PL17767925T PL17767925T PL3308469T3 PL 3308469 T3 PL3308469 T3 PL 3308469T3 PL 17767925 T PL17767925 T PL 17767925T PL 17767925 T PL17767925 T PL 17767925T PL 3308469 T3 PL3308469 T3 PL 3308469T3
Authority
PL
Poland
Prior art keywords
rate matching
ldpc codes
matching methods
methods
ldpc
Prior art date
Application number
PL17767925T
Other languages
English (en)
Inventor
Mattias Andersson
Yufei Blankenship
Sara SANDBERG
Original Assignee
Telefonaktiebolaget Lm Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Publication of PL3308469T3 publication Critical patent/PL3308469T3/pl

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Optical Communication System (AREA)
PL17767925T 2016-08-12 2017-08-10 Sposoby dopasowywania szybkości dla kodów LDPC PL3308469T3 (pl)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662374688P 2016-08-12 2016-08-12
PCT/IB2017/054889 WO2018029633A1 (en) 2016-08-12 2017-08-10 Rate matching methods for ldpc codes
EP17767925.5A EP3308469B1 (en) 2016-08-12 2017-08-10 Rate matching methods for ldpc codes

Publications (1)

Publication Number Publication Date
PL3308469T3 true PL3308469T3 (pl) 2020-08-24

Family

ID=59859415

Family Applications (1)

Application Number Title Priority Date Filing Date
PL17767925T PL3308469T3 (pl) 2016-08-12 2017-08-10 Sposoby dopasowywania szybkości dla kodów LDPC

Country Status (16)

Country Link
US (5) US10516419B2 (pl)
EP (2) EP3681041B1 (pl)
JP (1) JP6810790B2 (pl)
KR (1) KR102126404B1 (pl)
CN (2) CN116827356A (pl)
BR (1) BR112019002500A2 (pl)
CA (1) CA3031610C (pl)
CO (1) CO2019001225A2 (pl)
DK (1) DK3308469T3 (pl)
ES (2) ES2931850T3 (pl)
FI (1) FI3681041T3 (pl)
HU (1) HUE060810T2 (pl)
PL (1) PL3308469T3 (pl)
PT (1) PT3308469T (pl)
RU (1) RU2730434C1 (pl)
WO (1) WO2018029633A1 (pl)

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US10972219B2 (en) * 2018-09-24 2021-04-06 Qualcomm Incorporated LDPC interleaver design for improved error floor performance
WO2020132873A1 (zh) * 2018-12-25 2020-07-02 北京小米移动软件有限公司 数据传输方法及装置
US10877729B2 (en) 2019-01-31 2020-12-29 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Reconfigurable segmented scalable shifter
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CN113114271A (zh) * 2021-03-11 2021-07-13 苏州华兴源创科技股份有限公司 低密度奇偶校验编码装置和方法
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US7346832B2 (en) * 2004-07-21 2008-03-18 Qualcomm Incorporated LDPC encoding methods and apparatus
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Also Published As

Publication number Publication date
CA3031610A1 (en) 2018-02-15
CN116827356A (zh) 2023-09-29
PT3308469T (pt) 2020-06-02
CA3031610C (en) 2021-05-18
RU2730434C1 (ru) 2020-08-21
JP2019534588A (ja) 2019-11-28
EP3308469B1 (en) 2020-03-11
DK3308469T3 (da) 2020-06-02
JP6810790B2 (ja) 2021-01-06
ES2787907T3 (es) 2020-10-19
BR112019002500A2 (pt) 2019-05-14
CN110326220B (zh) 2023-06-02
US20240120950A1 (en) 2024-04-11
US11588504B2 (en) 2023-02-21
WO2018029633A1 (en) 2018-02-15
EP3681041B1 (en) 2022-10-26
US20190052290A1 (en) 2019-02-14
KR102126404B1 (ko) 2020-06-24
CN110326220A (zh) 2019-10-11
KR20190030213A (ko) 2019-03-21
EP3681041A1 (en) 2020-07-15
US20230179230A1 (en) 2023-06-08
US11870464B2 (en) 2024-01-09
US20200083913A1 (en) 2020-03-12
HUE060810T2 (hu) 2023-04-28
FI3681041T3 (fi) 2022-12-15
CO2019001225A2 (es) 2019-02-19
US10516419B2 (en) 2019-12-24
ES2931850T3 (es) 2023-01-03
US20210266017A1 (en) 2021-08-26
US11031960B2 (en) 2021-06-08
EP3308469A1 (en) 2018-04-18

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