NO922091L - Pc med foregripende lagerstyrings-signalisering - Google Patents

Pc med foregripende lagerstyrings-signalisering

Info

Publication number
NO922091L
NO922091L NO92922091A NO922091A NO922091L NO 922091 L NO922091 L NO 922091L NO 92922091 A NO92922091 A NO 92922091A NO 922091 A NO922091 A NO 922091A NO 922091 L NO922091 L NO 922091L
Authority
NO
Norway
Prior art keywords
bus
local processor
input
arbitration
volatile memory
Prior art date
Application number
NO92922091A
Other languages
English (en)
Norwegian (no)
Other versions
NO922091D0 (no
Inventor
Daniel Paul Fuoco
Luis Antonio Hernandez
Eric Mathisen
Dennis Lee Moeller
Jonathan Henry Raymond
Esmaeil Tashakori
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of NO922091D0 publication Critical patent/NO922091D0/no
Publication of NO922091L publication Critical patent/NO922091L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Absorbent Articles And Supports Therefor (AREA)
NO92922091A 1991-05-28 1992-05-26 Pc med foregripende lagerstyrings-signalisering NO922091L (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/706,534 US5353417A (en) 1991-05-28 1991-05-28 Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access

Publications (2)

Publication Number Publication Date
NO922091D0 NO922091D0 (no) 1992-05-26
NO922091L true NO922091L (no) 1992-11-30

Family

ID=24838034

Family Applications (1)

Application Number Title Priority Date Filing Date
NO92922091A NO922091L (no) 1991-05-28 1992-05-26 Pc med foregripende lagerstyrings-signalisering

Country Status (12)

Country Link
US (1) US5353417A (ja)
EP (1) EP0518503A1 (ja)
JP (1) JPH0769884B2 (ja)
KR (1) KR950008231B1 (ja)
CN (1) CN1029166C (ja)
AU (1) AU660667B2 (ja)
BR (1) BR9201974A (ja)
CA (1) CA2067602C (ja)
FI (1) FI922350A (ja)
MY (1) MY108101A (ja)
NO (1) NO922091L (ja)
SG (1) SG42881A1 (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2065989C (en) * 1991-06-07 1998-03-31 Don Steven Keener Personal computer data flow control
JP3515142B2 (ja) * 1992-06-11 2004-04-05 セイコーエプソン株式会社 データ転送制御装置
US6401158B1 (en) * 1993-07-16 2002-06-04 Compaq Computer Corporation Apparatus for providing a CPU cluster via a disk I/O bus using a CPU brick which fits into a disk cavity
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US5426740A (en) * 1994-01-14 1995-06-20 Ast Research, Inc. Signaling protocol for concurrent bus access in a multiprocessor system
US5546547A (en) * 1994-01-28 1996-08-13 Apple Computer, Inc. Memory bus arbiter for a computer system having a dsp co-processor
US5632020A (en) * 1994-03-25 1997-05-20 Advanced Micro Devices, Inc. System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking
US5721882A (en) * 1994-08-05 1998-02-24 Intel Corporation Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
US5513302A (en) * 1994-11-21 1996-04-30 Winbond Electronics Corp. Dual purpose printer interface device capable of connecting a printer and a joystick to a portable host computer
US5687393A (en) * 1995-06-07 1997-11-11 International Business Machines Corporation System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters
JPH11513150A (ja) * 1995-06-15 1999-11-09 インテル・コーポレーション Ｐｃｉ間ブリッジを統合する入出力プロセッサ用アーキテクチャ
US6324592B1 (en) 1997-02-25 2001-11-27 Keystone Aerospace Apparatus and method for a mobile computer architecture and input/output management system
US6115551A (en) * 1997-03-27 2000-09-05 Industrial Technology Research Institute System for minimizing the number of control signals and maximizing channel utilization between an I/O bridge and a data buffer
US6317801B1 (en) * 1998-07-27 2001-11-13 Intel Corporation System for post-driving and pre-driving bus agents on a terminated data bus
US6519666B1 (en) * 1999-10-05 2003-02-11 International Business Machines Corporation Arbitration scheme for optimal performance
JP2002041445A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
US20020161978A1 (en) * 2001-02-28 2002-10-31 George Apostol Multi-service system-on-chip including on-chip memory with multiple access path

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623986A (en) * 1984-02-23 1986-11-18 Texas Instruments Incorporated Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle
US4701843A (en) * 1985-04-01 1987-10-20 Ncr Corporation Refresh system for a page addressable memory
US4719621A (en) * 1985-07-15 1988-01-12 Raytheon Company Packet fastbus
JPS62190999U (ja) * 1986-05-23 1987-12-04
US5029074A (en) * 1987-06-29 1991-07-02 Digital Equipment Corporation Bus adapter unit for digital processing system
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
JPH077955B2 (ja) * 1989-05-13 1995-01-30 株式会社東芝 データ通信制御装置
US5220651A (en) * 1989-10-11 1993-06-15 Micral, Inc. Cpu-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus
US5202857A (en) * 1990-11-07 1993-04-13 Emc Corporation System for generating memory timing and reducing memory access time

Also Published As

Publication number Publication date
FI922350A (fi) 1992-11-29
CN1029166C (zh) 1995-06-28
KR920022113A (ko) 1992-12-19
JPH0769884B2 (ja) 1995-07-31
US5353417A (en) 1994-10-04
CN1067126A (zh) 1992-12-16
CA2067602C (en) 1998-05-05
KR950008231B1 (ko) 1995-07-26
FI922350A0 (fi) 1992-05-22
EP0518503A1 (en) 1992-12-16
SG42881A1 (en) 1997-10-17
CA2067602A1 (en) 1992-11-29
NO922091D0 (no) 1992-05-26
AU1520092A (en) 1992-12-03
MY108101A (en) 1996-08-15
JPH05197672A (ja) 1993-08-06
AU660667B2 (en) 1995-07-06
BR9201974A (pt) 1993-01-12

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