NO913707L - Anordning og fremgangsmaate for optimalisering av buss-arbitrering. - Google Patents
Anordning og fremgangsmaate for optimalisering av buss-arbitrering.Info
- Publication number
- NO913707L NO913707L NO91913707A NO913707A NO913707L NO 913707 L NO913707 L NO 913707L NO 91913707 A NO91913707 A NO 91913707A NO 913707 A NO913707 A NO 913707A NO 913707 L NO913707 L NO 913707L
- Authority
- NO
- Norway
- Prior art keywords
- bus
- priority
- arbitrary
- external devices
- master
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Abstract
Anordning og fremgangsmåte for å optimalisere buss- arbitræring l løpet av direkte lageraksess (DMA) dataoverføring over en ikke-dedikert buss mellom et lager og/eller flere eksterne anordninger hvor hver master har en arbitrær prioritet. I det minste to ikke- overlappende klokker (Cl, C2) er anordnet pr. over- førlngssyklus og der er i det minste en overførings- syklus pr. arbitrær syklus. Arbitrærprioritets- anmodningen sendes for hver ekstern anordning (13, 14) til en arbitrær buss (12) kun ved stigning av den første klokken. Ved slutten av den siste klokken blir prioritetskoden til den eksterne anordningen som har høyest prioritet bestemt for å designere den eksterne anordningen som skal bil bussmaster. Adresser og data blir overført mellom den designerte bussmasteren og lageret eller en annen av de eksterne anordningene via den Ikke-dedikerte bussen i løpet av neste syklus etter en for øyeblikket aktiv bussmaster avgir styringen.^ Prioriteten til de eksterne anordningene (13, 14) kan bil endret dynamisk. Arbltrærsyklusene blir parallellutført på en slik måte at det ikke er noe tap av adresse eller dataover- føringssykluser. Den for øyeblikket aktive bussmasteren kan utvide antall sykluser l løpet av hvilke de kommuniserer med en eller flere eksterne anordninger (13, 14). En anordning betegnet som neste i linjen som bussmaster kan bli fortømt under visse betingelser.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58634990A | 1990-09-21 | 1990-09-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
NO913707D0 NO913707D0 (no) | 1991-09-20 |
NO913707L true NO913707L (no) | 1992-03-23 |
Family
ID=24345380
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO91913707A NO913707L (no) | 1990-09-21 | 1991-09-20 | Anordning og fremgangsmaate for optimalisering av buss-arbitrering. |
Country Status (18)
Country | Link |
---|---|
US (1) | US5195185A (no) |
EP (1) | EP0476990B1 (no) |
JP (1) | JPH0810445B2 (no) |
KR (1) | KR950014505B1 (no) |
CN (1) | CN1037553C (no) |
AU (1) | AU639589B2 (no) |
BR (1) | BR9103929A (no) |
CA (1) | CA2050129C (no) |
CZ (1) | CZ282214B6 (no) |
DE (1) | DE69132344T2 (no) |
FI (1) | FI914429A (no) |
HU (1) | HU215867B (no) |
MX (1) | MX173460B (no) |
NO (1) | NO913707L (no) |
PL (1) | PL167608B1 (no) |
PT (1) | PT99006A (no) |
RU (1) | RU2110838C1 (no) |
SG (1) | SG42853A1 (no) |
Families Citing this family (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5559962A (en) * | 1989-10-09 | 1996-09-24 | Yamaha Corporation | Data transmission system selecting both source and destination using addressing mechanism |
US5461723A (en) * | 1990-04-05 | 1995-10-24 | Mit Technology Corp. | Dual channel data block transfer bus |
FR2675286B1 (fr) * | 1991-04-15 | 1993-06-18 | Bull Sa | Circuit integre arbitreur de bus mca et utilisations d'un tel circuit. |
US5454082A (en) * | 1991-09-18 | 1995-09-26 | Ncr Corporation | System for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second bus |
JPH05165762A (ja) * | 1991-12-13 | 1993-07-02 | Toshiba Corp | Dmaコントローラ |
DE69320508T2 (de) * | 1992-03-04 | 1999-03-04 | Motorola Inc | Verfahren und Gerät zur Busarbitrierungsdurchführung mit einem Arbiter in einem Datenverarbeitungssystem |
DE69319763T2 (de) * | 1992-03-04 | 1999-03-11 | Motorola Inc | Verfahren und Gerät zur Durchführung eines Busarbitrierungsprotokolls in einem Datenverarbeitungssystem |
US5341480A (en) * | 1992-04-09 | 1994-08-23 | Apple Computer, Inc. | Method and apparatus for providing a two conductor serial bus |
JPH05342178A (ja) * | 1992-06-10 | 1993-12-24 | Hitachi Ltd | 調停回路およびそれを用いたデータ処理装置 |
US5313591A (en) * | 1992-06-25 | 1994-05-17 | Hewlett-Packard Company | Computer bus arbitration for N processors requiring only N unidirectional signal leads |
US5596749A (en) * | 1992-09-21 | 1997-01-21 | Texas Instruments Incorporated | Arbitration request sequencer |
US5535395A (en) * | 1992-10-02 | 1996-07-09 | Compaq Computer Corporation | Prioritization of microprocessors in multiprocessor computer systems |
US5553248A (en) * | 1992-10-02 | 1996-09-03 | Compaq Computer Corporation | System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal |
US5553310A (en) * | 1992-10-02 | 1996-09-03 | Compaq Computer Corporation | Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems |
US5299196A (en) * | 1992-11-12 | 1994-03-29 | International Business Machines Corporation | Distributed address decoding for bus structures |
JPH06282528A (ja) * | 1993-01-29 | 1994-10-07 | Internatl Business Mach Corp <Ibm> | データ転送方法及びそのシステム |
US5546548A (en) * | 1993-03-31 | 1996-08-13 | Intel Corporation | Arbiter and arbitration process for a dynamic and flexible prioritization |
EP0619547A1 (en) * | 1993-04-05 | 1994-10-12 | Motorola, Inc. | A method of requesting data and apparatus therefor |
CA2115731C (en) * | 1993-05-17 | 2000-01-25 | Mikiel Loyal Larson | Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction |
US5517671A (en) * | 1993-07-30 | 1996-05-14 | Dell Usa, L.P. | System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus |
US6163848A (en) * | 1993-09-22 | 2000-12-19 | Advanced Micro Devices, Inc. | System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus |
US5600839A (en) * | 1993-10-01 | 1997-02-04 | Advanced Micro Devices, Inc. | System and method for controlling assertion of a peripheral bus clock signal through a slave device |
US5524215A (en) * | 1993-10-05 | 1996-06-04 | Motorola, Inc. | Bus protocol and method for controlling a data processor |
EP0654743A1 (en) * | 1993-11-19 | 1995-05-24 | International Business Machines Corporation | Computer system having a DSP local bus |
US5519838A (en) * | 1994-02-24 | 1996-05-21 | Hewlett-Packard Company | Fast pipelined distributed arbitration scheme |
US6026455A (en) * | 1994-02-24 | 2000-02-15 | Intel Corporation | Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system |
US5533205A (en) * | 1994-03-30 | 1996-07-02 | International Business Machines Corporation | Method and system for efficient bus allocation in a multimedia computer system |
US5526496A (en) * | 1994-04-22 | 1996-06-11 | The University Of British Columbia | Method and apparatus for priority arbitration among devices in a computer system |
US5572687A (en) * | 1994-04-22 | 1996-11-05 | The University Of British Columbia | Method and apparatus for priority arbitration among devices in a computer system |
US5758106A (en) * | 1994-06-30 | 1998-05-26 | Digital Equipment Corporation | Arbitration unit which requests control of the system bus prior to determining whether such control is required |
US6256694B1 (en) * | 1994-06-30 | 2001-07-03 | Compaq Computer Corporation | Distributed early arbitration |
US5568614A (en) * | 1994-07-29 | 1996-10-22 | International Business Machines Corporation | Data streaming between peer subsystems of a computer system |
US5598542A (en) * | 1994-08-08 | 1997-01-28 | International Business Machines Corporation | Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values |
US5559969A (en) * | 1994-08-09 | 1996-09-24 | Unisys Corporation | Method and apparatus for efficiently interfacing variable width data streams to a fixed width memory |
US5634060A (en) * | 1994-08-09 | 1997-05-27 | Unisys Corporation | Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus |
US6434638B1 (en) | 1994-12-09 | 2002-08-13 | International Business Machines Corporation | Arbitration protocol for peer-to-peer communication in synchronous systems |
KR0155269B1 (ko) * | 1995-01-16 | 1998-11-16 | 김광호 | 버스 중재방법 및 그 장치 |
JP3320233B2 (ja) * | 1995-02-06 | 2002-09-03 | キヤノン株式会社 | 記録装置 |
US5701313A (en) * | 1995-02-24 | 1997-12-23 | Unisys Corporation | Method and apparatus for removing soft errors from a memory |
US5511164A (en) | 1995-03-01 | 1996-04-23 | Unisys Corporation | Method and apparatus for determining the source and nature of an error within a computer system |
US5740383A (en) * | 1995-12-22 | 1998-04-14 | Cirrus Logic, Inc. | Dynamic arbitration priority |
KR100201325B1 (ko) * | 1996-03-30 | 1999-06-15 | 유기범 | 다중 프로세서 시스템에서 시스템 버스의 클럭속도를 향상시키는 방법 |
US5842025A (en) * | 1996-08-27 | 1998-11-24 | Mmc Networks, Inc. | Arbitration methods and apparatus |
US5970253A (en) * | 1997-01-09 | 1999-10-19 | Unisys Corporation | Priority logic for selecting and stacking data |
US5822766A (en) * | 1997-01-09 | 1998-10-13 | Unisys Corporation | Main memory interface for high speed data transfer |
US5859986A (en) * | 1997-02-20 | 1999-01-12 | International Business Machines Corporation | Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing |
US5862353A (en) * | 1997-03-25 | 1999-01-19 | International Business Machines Corporation | Systems and methods for dynamically controlling a bus |
US5996037A (en) * | 1997-06-03 | 1999-11-30 | Lsi Logic Corporation | System and method for arbitrating multi-function access to a system bus |
US6006303A (en) * | 1997-08-28 | 1999-12-21 | Oki Electric Industry Co., Inc. | Priority encoding and decoding for memory architecture |
JP4019333B2 (ja) * | 1998-02-13 | 2007-12-12 | 富士通株式会社 | ヘッドic回路及び記録装置 |
US6047336A (en) * | 1998-03-16 | 2000-04-04 | International Business Machines Corporation | Speculative direct memory access transfer between slave devices and memory |
US6182112B1 (en) | 1998-06-12 | 2001-01-30 | Unisys Corporation | Method of and apparatus for bandwidth control of transfers via a bi-directional interface |
US6199135B1 (en) | 1998-06-12 | 2001-03-06 | Unisys Corporation | Source synchronous transfer scheme for a high speed memory interface |
US6330646B1 (en) * | 1999-01-08 | 2001-12-11 | Intel Corporation | Arbitration mechanism for a computer system having a unified memory architecture |
US6519666B1 (en) | 1999-10-05 | 2003-02-11 | International Business Machines Corporation | Arbitration scheme for optimal performance |
US8834864B2 (en) * | 2003-06-05 | 2014-09-16 | Baxter International Inc. | Methods for repairing and regenerating human dura mater |
KR101034493B1 (ko) * | 2004-01-09 | 2011-05-17 | 삼성전자주식회사 | 화상 변환 장치, 화상 변환을 위한 직접 메모리 액세스장치 및 화상 변환을 지원하는 카메라 인터페이스 |
JP2006155387A (ja) * | 2004-11-30 | 2006-06-15 | Yamaha Corp | コンピュータシステム |
DE602006019005D1 (de) * | 2006-06-27 | 2011-01-27 | Thomson Licensing | Verfahren und vorrichtung zur durchführung der arbitrierung |
GB2473505B (en) * | 2009-09-15 | 2016-09-14 | Advanced Risc Mach Ltd | A data processing apparatus and a method for setting priority levels for transactions |
US8713277B2 (en) * | 2010-06-01 | 2014-04-29 | Apple Inc. | Critical word forwarding with adaptive prediction |
CN111478840A (zh) * | 2020-04-15 | 2020-07-31 | 联合华芯电子有限公司 | 用于总线系统的双速率仲裁中继设备 |
CN113821470A (zh) * | 2020-06-19 | 2021-12-21 | 平头哥(上海)半导体技术有限公司 | 总线设备、嵌入式系统和片上系统 |
RU2749911C1 (ru) * | 2020-12-25 | 2021-06-21 | Акционерное Общество "Крафтвэй Корпорэйшн Плс" | Аппаратная реализация механизма использования одной памяти несколькими устройствами |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4481580A (en) * | 1979-11-19 | 1984-11-06 | Sperry Corporation | Distributed data transfer control for parallel processor architectures |
US4453211A (en) * | 1981-04-28 | 1984-06-05 | Formation, Inc. | System bus for an emulated multichannel system |
EP0340347B1 (en) * | 1983-09-22 | 1994-04-06 | Digital Equipment Corporation | Bus arbitration system |
US4967344A (en) * | 1985-03-26 | 1990-10-30 | Codex Corporation | Interconnection network for multiple processors |
US4837677A (en) * | 1985-06-14 | 1989-06-06 | International Business Machines Corporation | Multiple port service expansion adapter for a communications controller |
US4924427A (en) * | 1985-11-15 | 1990-05-08 | Unisys Corporation | Direct memory access controller with direct memory to memory transfers |
US4949301A (en) * | 1986-03-06 | 1990-08-14 | Advanced Micro Devices, Inc. | Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs |
JPS6366654A (ja) * | 1986-09-08 | 1988-03-25 | Matsushita Electric Ind Co Ltd | 同期型バス |
US4947368A (en) * | 1987-05-01 | 1990-08-07 | Digital Equipment Corporation | Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers |
EP0321628B1 (en) * | 1987-12-23 | 1992-11-04 | International Business Machines Corporation | Shared memory interface for a data processing system |
US5001625A (en) * | 1988-03-24 | 1991-03-19 | Gould Inc. | Bus structure for overlapped data transfer |
US5016162A (en) * | 1988-03-30 | 1991-05-14 | Data General Corp. | Contention revolution in a digital computer system |
US4987529A (en) * | 1988-08-11 | 1991-01-22 | Ast Research, Inc. | Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters |
US5006982A (en) * | 1988-10-21 | 1991-04-09 | Siemens Ak. | Method of increasing the bandwidth of a packet bus by reordering reply packets |
-
1991
- 1991-07-18 JP JP3202231A patent/JPH0810445B2/ja not_active Expired - Lifetime
- 1991-08-21 CN CN91105822A patent/CN1037553C/zh not_active Expired - Fee Related
- 1991-08-21 KR KR1019910014385A patent/KR950014505B1/ko not_active IP Right Cessation
- 1991-08-21 AU AU82612/91A patent/AU639589B2/en not_active Ceased
- 1991-08-28 CA CA002050129A patent/CA2050129C/en not_active Expired - Fee Related
- 1991-09-12 BR BR919103929A patent/BR9103929A/pt unknown
- 1991-09-18 SG SG1996000146A patent/SG42853A1/en unknown
- 1991-09-18 DE DE69132344T patent/DE69132344T2/de not_active Expired - Fee Related
- 1991-09-18 EP EP91308506A patent/EP0476990B1/en not_active Expired - Lifetime
- 1991-09-19 PT PT99006A patent/PT99006A/pt not_active Application Discontinuation
- 1991-09-19 MX MX9101149A patent/MX173460B/es unknown
- 1991-09-19 PL PL91291778A patent/PL167608B1/pl unknown
- 1991-09-20 CZ CS912874A patent/CZ282214B6/cs not_active IP Right Cessation
- 1991-09-20 NO NO91913707A patent/NO913707L/no unknown
- 1991-09-20 HU HU913024A patent/HU215867B/hu unknown
- 1991-09-20 RU SU5001612A patent/RU2110838C1/ru active
- 1991-09-20 FI FI914429A patent/FI914429A/fi not_active Application Discontinuation
-
1992
- 1992-02-21 US US07/841,227 patent/US5195185A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
PT99006A (pt) | 1993-10-29 |
EP0476990B1 (en) | 2000-08-02 |
HUT58931A (en) | 1992-03-30 |
EP0476990A2 (en) | 1992-03-25 |
EP0476990A3 (en) | 1993-08-04 |
PL167608B1 (pl) | 1995-09-30 |
CA2050129A1 (en) | 1992-03-22 |
CN1037553C (zh) | 1998-02-25 |
NO913707D0 (no) | 1991-09-20 |
CS287491A3 (en) | 1992-04-15 |
FI914429A0 (fi) | 1991-09-20 |
US5195185A (en) | 1993-03-16 |
MX173460B (es) | 1994-03-04 |
JPH04246758A (ja) | 1992-09-02 |
CN1060166A (zh) | 1992-04-08 |
CA2050129C (en) | 1996-05-14 |
AU639589B2 (en) | 1993-07-29 |
DE69132344D1 (de) | 2000-09-07 |
PL291778A1 (en) | 1992-06-01 |
HU215867B (hu) | 1999-03-29 |
KR920006858A (ko) | 1992-04-28 |
FI914429A (fi) | 1992-03-22 |
DE69132344T2 (de) | 2001-02-15 |
RU2110838C1 (ru) | 1998-05-10 |
KR950014505B1 (ko) | 1995-12-02 |
JPH0810445B2 (ja) | 1996-01-31 |
CZ282214B6 (cs) | 1997-06-11 |
HU913024D0 (en) | 1992-01-28 |
SG42853A1 (en) | 1997-10-17 |
BR9103929A (pt) | 1992-05-26 |
AU8261291A (en) | 1992-03-26 |
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