NO20015509D0 - Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte - Google Patents

Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte

Info

Publication number
NO20015509D0
NO20015509D0 NO20015509A NO20015509A NO20015509D0 NO 20015509 D0 NO20015509 D0 NO 20015509D0 NO 20015509 A NO20015509 A NO 20015509A NO 20015509 A NO20015509 A NO 20015509A NO 20015509 D0 NO20015509 D0 NO 20015509D0
Authority
NO
Norway
Prior art keywords
electrodes
electrode layers
electrode
addressable
matrix
Prior art date
Application number
NO20015509A
Other languages
English (en)
Norwegian (no)
Inventor
Hans Gude Gudesen
Original Assignee
Hans Gude Gudesen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hans Gude Gudesen filed Critical Hans Gude Gudesen
Priority to NO20015509A priority Critical patent/NO20015509D0/no
Publication of NO20015509D0 publication Critical patent/NO20015509D0/no
Priority to CA002466267A priority patent/CA2466267C/en
Priority to AT02778118T priority patent/ATE295990T1/de
Priority to AU2002339770A priority patent/AU2002339770B2/en
Priority to RU2004116275/09A priority patent/RU2275697C2/ru
Priority to JP2003543032A priority patent/JP2005509282A/ja
Priority to ES02778118T priority patent/ES2242883T3/es
Priority to CNA028220994A priority patent/CN1582481A/zh
Priority to NO20025380A priority patent/NO322262B1/no
Priority to US10/290,524 priority patent/US6833593B2/en
Priority to DK02778118T priority patent/DK1446805T3/da
Priority to KR1020047007005A priority patent/KR100577544B1/ko
Priority to EP02778118A priority patent/EP1446805B8/en
Priority to DE60204239T priority patent/DE60204239T2/de
Priority to PCT/NO2002/000414 priority patent/WO2003041084A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/202—Integrated devices comprising a common active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Electrolytic Production Of Metals (AREA)
  • Liquid Crystal (AREA)
NO20015509A 2001-11-09 2001-11-09 Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte NO20015509D0 (no)

Priority Applications (15)

Application Number Priority Date Filing Date Title
NO20015509A NO20015509D0 (no) 2001-11-09 2001-11-09 Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte
PCT/NO2002/000414 WO2003041084A1 (en) 2001-11-09 2002-11-08 Electrodes, method and apparatus for memory structure
ES02778118T ES2242883T3 (es) 2001-11-09 2002-11-08 Electrodos, procedimiento y aparato para una estructura de memoria.
NO20025380A NO322262B1 (no) 2001-11-09 2002-11-08 Elektrodeanordning, fremgangsmate til dens fremstilling, et apparat som omfatter elektrodeanordningen samt bruk av den sistnevnte
AU2002339770A AU2002339770B2 (en) 2001-11-09 2002-11-08 Electrodes, method and apparatus for memory structure
RU2004116275/09A RU2275697C2 (ru) 2001-11-09 2002-11-08 Электродная решетка, способ ее изготовления и устройство обработки и/или хранения данных
JP2003543032A JP2005509282A (ja) 2001-11-09 2002-11-08 メモリ構造体用電極、方法および装置
CA002466267A CA2466267C (en) 2001-11-09 2002-11-08 Electrodes, method and apparatus for memory structure
CNA028220994A CN1582481A (zh) 2001-11-09 2002-11-08 存储结构的电极、方法和设备
AT02778118T ATE295990T1 (de) 2001-11-09 2002-11-08 Elektroden, verfahren und vorrichtung für eine speicherstruktur
US10/290,524 US6833593B2 (en) 2001-11-09 2002-11-08 Electrode means, a method for its manufacture, an apparatus comprising the electrode means as well as use of the latter
DK02778118T DK1446805T3 (da) 2001-11-09 2002-11-08 Elektroder, fremgangsmåde og apparatur til en hukommelsesstruktur
KR1020047007005A KR100577544B1 (ko) 2001-11-09 2002-11-08 메모리 구조물을 위한 전극들, 방법 및 장치
EP02778118A EP1446805B8 (en) 2001-11-09 2002-11-08 Electrodes, method and apparatus for memory structure
DE60204239T DE60204239T2 (de) 2001-11-09 2002-11-08 Elektroden, verfahren und vorrichtung für eine speicherstruktur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NO20015509A NO20015509D0 (no) 2001-11-09 2001-11-09 Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte

Publications (1)

Publication Number Publication Date
NO20015509D0 true NO20015509D0 (no) 2001-11-09

Family

ID=19913010

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20015509A NO20015509D0 (no) 2001-11-09 2001-11-09 Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte

Country Status (12)

Country Link
EP (1) EP1446805B8 (enExample)
JP (1) JP2005509282A (enExample)
KR (1) KR100577544B1 (enExample)
CN (1) CN1582481A (enExample)
AT (1) ATE295990T1 (enExample)
AU (1) AU2002339770B2 (enExample)
CA (1) CA2466267C (enExample)
DE (1) DE60204239T2 (enExample)
ES (1) ES2242883T3 (enExample)
NO (1) NO20015509D0 (enExample)
RU (1) RU2275697C2 (enExample)
WO (1) WO2003041084A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833593B2 (en) 2001-11-09 2004-12-21 Thin Film Electronics Asa Electrode means, a method for its manufacture, an apparatus comprising the electrode means as well as use of the latter
US6724028B2 (en) 2001-12-10 2004-04-20 Hans Gude Gudesen Matrix-addressable array of integrated transistor/memory structures
US6649504B2 (en) 2001-12-14 2003-11-18 Thin Film Electronics Asa Method for fabricating high aspect ratio electrodes
NO321280B1 (no) 2004-07-22 2006-04-18 Thin Film Electronics Asa Organisk, elektronisk krets og fremgangsmate til dens fremstilling
US7808024B2 (en) * 2004-09-27 2010-10-05 Intel Corporation Ferroelectric polymer memory module
WO2014158187A1 (en) * 2013-03-29 2014-10-02 Applied Materials, Inc. Substrate imprinted with a pattern for forming isolated device regions
US10199386B2 (en) * 2015-07-23 2019-02-05 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same
KR102408494B1 (ko) * 2019-08-13 2022-06-15 브이메모리 주식회사 전기장을 이용한 전류 경로 제어 방법 및 전자 소자
CN114582632B (zh) * 2022-01-11 2024-05-17 华东师范大学 一种应用于动态目标提取的铁电电容阵列及其制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4952031A (en) * 1987-06-19 1990-08-28 Victor Company Of Japan, Ltd. Liquid crystal display device
US5017515A (en) * 1989-10-02 1991-05-21 Texas Instruments Incorporated Process for minimizing lateral distance between elements in an integrated circuit by using sidewall spacers
JPH07106450A (ja) * 1993-10-08 1995-04-21 Olympus Optical Co Ltd 強誘電体ゲートトランジスタメモリ
NO972803D0 (no) * 1997-06-17 1997-06-17 Opticom As Elektrisk adresserbar logisk innretning, fremgangsmåte til elektrisk adressering av samme og anvendelse av innretning og fremgangsmåte
DE69739045D1 (de) * 1997-08-27 2008-11-27 St Microelectronics Srl Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse
US6072716A (en) * 1999-04-14 2000-06-06 Massachusetts Institute Of Technology Memory structures and methods of making same
US6473388B1 (en) * 2000-08-31 2002-10-29 Hewlett Packard Company Ultra-high density information storage device based on modulated cathodoconductivity

Also Published As

Publication number Publication date
CN1582481A (zh) 2005-02-16
RU2275697C2 (ru) 2006-04-27
DE60204239T2 (de) 2006-01-26
CA2466267A1 (en) 2003-05-15
ATE295990T1 (de) 2005-06-15
EP1446805A1 (en) 2004-08-18
AU2002339770B2 (en) 2006-01-05
DE60204239D1 (de) 2005-06-23
RU2004116275A (ru) 2005-10-27
ES2242883T3 (es) 2005-11-16
EP1446805B8 (en) 2006-06-14
KR20040063929A (ko) 2004-07-14
JP2005509282A (ja) 2005-04-07
KR100577544B1 (ko) 2006-05-10
CA2466267C (en) 2006-05-23
WO2003041084A1 (en) 2003-05-15
EP1446805B1 (en) 2005-05-18

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