NL8800903A - Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden. - Google Patents

Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden. Download PDF

Info

Publication number
NL8800903A
NL8800903A NL8800903A NL8800903A NL8800903A NL 8800903 A NL8800903 A NL 8800903A NL 8800903 A NL8800903 A NL 8800903A NL 8800903 A NL8800903 A NL 8800903A NL 8800903 A NL8800903 A NL 8800903A
Authority
NL
Netherlands
Prior art keywords
layer
substrate
silicon
oxidation
mask
Prior art date
Application number
NL8800903A
Other languages
English (en)
Dutch (nl)
Inventor
Herbert Lifka
Pierre Hermanus Woerlee
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Priority to NL8800903A priority Critical patent/NL8800903A/nl
Priority to DE68929332T priority patent/DE68929332T2/de
Priority to EP89200845A priority patent/EP0336515B1/fr
Priority to JP1085860A priority patent/JPH0212822A/ja
Priority to KR1019890004648A priority patent/KR890016656A/ko
Publication of NL8800903A publication Critical patent/NL8800903A/nl

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
NL8800903A 1988-04-08 1988-04-08 Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden. NL8800903A (nl)

Priority Applications (5)

Application Number Priority Date Filing Date Title
NL8800903A NL8800903A (nl) 1988-04-08 1988-04-08 Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden.
DE68929332T DE68929332T2 (de) 1988-04-08 1989-04-03 Verfahren zum Herstellen einer Halbleiteranordnung mit einem Siliziumsubstrat mit völlig oder teilweise versenkten Feldoxidigebieten
EP89200845A EP0336515B1 (fr) 1988-04-08 1989-04-03 Procédé de fabrication d'un dispositif semiconducteur muni d'un substrat de silicium présentant des régions d'oxyde d'isolement en tout ou en partie noyées
JP1085860A JPH0212822A (ja) 1988-04-08 1989-04-06 完全にまたは部分的に埋められたフィールド酸化物層を有する半導体デバイスの製造方法
KR1019890004648A KR890016656A (ko) 1988-04-08 1989-04-08 전체 또는 부분 함몰 전계 산화물 지역들을 갖춘 실리콘 기판을 갖고 있는 반도체 장치 제조방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8800903 1988-04-08
NL8800903A NL8800903A (nl) 1988-04-08 1988-04-08 Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden.

Publications (1)

Publication Number Publication Date
NL8800903A true NL8800903A (nl) 1989-11-01

Family

ID=19852091

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8800903A NL8800903A (nl) 1988-04-08 1988-04-08 Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden.

Country Status (5)

Country Link
EP (1) EP0336515B1 (fr)
JP (1) JPH0212822A (fr)
KR (1) KR890016656A (fr)
DE (1) DE68929332T2 (fr)
NL (1) NL8800903A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100197651B1 (ko) * 1995-11-03 1999-06-15 김영환 반도체 소자의 소자 분리막 제조방법
US5661072A (en) * 1996-05-23 1997-08-26 Micron Technology, Inc. Method for reducing oxide thinning during the formation of a semiconductor device
JP6258672B2 (ja) 2013-11-21 2018-01-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038110A (en) * 1974-06-17 1977-07-26 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4333965A (en) * 1980-09-15 1982-06-08 General Electric Company Method of making integrated circuits
JPS5821842A (ja) * 1981-07-30 1983-02-08 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン 分離領域の形成方法
NL8401711A (nl) * 1984-05-29 1985-12-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin plaatselijk een verzonken oxidelaag is aangebracht.
US4631219A (en) * 1985-01-31 1986-12-23 International Business Machines Corporation Growth of bird's beak free semi-rox
NL8501720A (nl) * 1985-06-14 1987-01-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een siliciumplak plaatselijk wordt voorzien van veldoxide met kanaalonderbreker.

Also Published As

Publication number Publication date
DE68929332T2 (de) 2002-07-04
JPH0212822A (ja) 1990-01-17
DE68929332D1 (de) 2001-11-22
KR890016656A (ko) 1989-11-29
EP0336515B1 (fr) 2001-10-17
EP0336515A1 (fr) 1989-10-11

Similar Documents

Publication Publication Date Title
US4333964A (en) Method of making integrated circuits
US4533429A (en) Method of manufacturing a semiconductor device
US4333965A (en) Method of making integrated circuits
CA1186600A (fr) Methode de formation de reseaux conducteurs sur substrats
JPS63107119A (ja) ステップ絶縁層を有する集積回路の製造方法
US4612701A (en) Method to reduce the height of the bird's head in oxide isolated processes
JPS63299144A (ja) パッド用酸化保護層でシールされたインターフェイス分離方法
US5397732A (en) PBLOCOS with sandwiched thin silicon nitride layer
NL8800903A (nl) Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden.
US4293588A (en) Method of manufacturing a semiconductor device using different etch rates
JPS6123657B2 (fr)
US6579766B1 (en) Dual gate oxide process without critical resist and without N2 implant
JPH0329296B2 (fr)
US4411929A (en) Method for manufacturing semiconductor device
US6265286B1 (en) Planarization of LOCOS through recessed reoxidation techniques
JP3862965B2 (ja) 加工方法
JPH07135247A (ja) 半導体装置の製造方法
JPH01184852A (ja) スペーサでマスクされたvlsiプロセス
JP3178444B2 (ja) 半導体装置の製造方法
KR960014453B1 (ko) 필드 산화막 제조방법
KR100266024B1 (ko) 반도체장치의소자격리방법
KR940010323B1 (ko) 반도체 장치의 제조방법
KR0142794B1 (ko) 반도체 소자의 격리막 형성방법
JPS61279689A (ja) 側壁保護膜を有したエツチングマスク構造とその製造方法
JPS6194338A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A1B A search report has been drawn up
BV The patent application has lapsed