NL8601694A - Werkwijze voor het vervaardigen van halfgeleider inrichtingen. - Google Patents

Werkwijze voor het vervaardigen van halfgeleider inrichtingen. Download PDF

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Publication number
NL8601694A
NL8601694A NL8601694A NL8601694A NL8601694A NL 8601694 A NL8601694 A NL 8601694A NL 8601694 A NL8601694 A NL 8601694A NL 8601694 A NL8601694 A NL 8601694A NL 8601694 A NL8601694 A NL 8601694A
Authority
NL
Netherlands
Prior art keywords
layer
stepped
etching
insulating layer
silicon nitride
Prior art date
Application number
NL8601694A
Other languages
English (en)
Dutch (nl)
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of NL8601694A publication Critical patent/NL8601694A/nl

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
NL8601694A 1985-06-28 1986-06-27 Werkwijze voor het vervaardigen van halfgeleider inrichtingen. NL8601694A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14294485 1985-06-28
JP14294485 1985-06-28

Publications (1)

Publication Number Publication Date
NL8601694A true NL8601694A (nl) 1987-01-16

Family

ID=15327276

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8601694A NL8601694A (nl) 1985-06-28 1986-06-27 Werkwijze voor het vervaardigen van halfgeleider inrichtingen.

Country Status (2)

Country Link
JP (1) JPH0779097B2 (ja)
NL (1) NL8601694A (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2564312B2 (ja) * 1987-07-17 1996-12-18 株式会社日立製作所 エッチング終点判定方法および装置
FR2627902B1 (fr) * 1988-02-26 1990-06-22 Philips Nv Procede pour aplanir la surface d'un dispositif semiconducteur
JPH02292841A (ja) * 1989-05-02 1990-12-04 Matsushita Electron Corp 半導体集積回路の平坦度評価方法
EP4152393A4 (en) * 2021-08-04 2024-01-03 Changxin Memory Technologies, Inc. SEMICONDUCTOR STRUCTURE AND PRODUCTION PROCESS THEREOF

Also Published As

Publication number Publication date
JPH0779097B2 (ja) 1995-08-23
JPS6290934A (ja) 1987-04-25

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BB A search report has been drawn up
BV The patent application has lapsed