NL6916239A - - Google Patents

Info

Publication number
NL6916239A
NL6916239A NL6916239A NL6916239A NL6916239A NL 6916239 A NL6916239 A NL 6916239A NL 6916239 A NL6916239 A NL 6916239A NL 6916239 A NL6916239 A NL 6916239A NL 6916239 A NL6916239 A NL 6916239A
Authority
NL
Netherlands
Application number
NL6916239A
Other versions
NL154868B (nl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL6916239A publication Critical patent/NL6916239A/xx
Publication of NL154868B publication Critical patent/NL154868B/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
NL696916239A 1968-10-28 1969-10-28 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen en halfgeleiderinrichtingen volgens deze werkwijze verkregen. NL154868B (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB5103568 1968-10-28
GB24991/69A GB1285708A (en) 1968-10-28 1968-10-28 Semi-conductor devices

Publications (2)

Publication Number Publication Date
NL6916239A true NL6916239A (enExample) 1970-05-01
NL154868B NL154868B (nl) 1977-10-17

Family

ID=26257416

Family Applications (1)

Application Number Title Priority Date Filing Date
NL696916239A NL154868B (nl) 1968-10-28 1969-10-28 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen en halfgeleiderinrichtingen volgens deze werkwijze verkregen.

Country Status (12)

Country Link
US (1) US3756872A (enExample)
AT (1) AT310253B (enExample)
BE (1) BE740836A (enExample)
CH (1) CH522955A (enExample)
CS (1) CS168552B2 (enExample)
DE (1) DE1954265A1 (enExample)
DK (1) DK135071B (enExample)
ES (2) ES373341A1 (enExample)
FR (1) FR2021690B1 (enExample)
GB (1) GB1285708A (enExample)
NL (1) NL154868B (enExample)
SE (2) SE363930B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2124772A1 (de) * 1970-05-21 1971-12-02 Lucas Ltd Joseph Verfahren zur Herstellung von Halb leiter Bauelementen
FR2100997A1 (enExample) * 1970-08-04 1972-03-31 Silec Semi Conducteurs

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527463B2 (enExample) * 1973-02-28 1980-07-21
IT1059086B (it) * 1976-04-14 1982-05-31 Ates Componenti Elettron Procedimento per la passivazione di dispositivi a semiconduttore di potenza ad alta tensione inversa
DE2929339A1 (de) * 1978-07-24 1980-02-14 Citizen Watch Co Ltd Halbleiteranordnung
US4624724A (en) * 1985-01-17 1986-11-25 General Electric Company Method of making integrated circuit silicon die composite having hot melt adhesive on its silicon base
DE3621796A1 (de) * 1986-06-30 1988-01-07 Siemens Ag Verfahren zur verbesserung der nebensprechdaempfung bei einer optisch-elektronischen sensoranordnung
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
US6864570B2 (en) * 1993-12-17 2005-03-08 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
US5545291A (en) * 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
US5904545A (en) * 1993-12-17 1999-05-18 The Regents Of The University Of California Apparatus for fabricating self-assembling microstructures
DE19604405C2 (de) * 1996-02-07 2002-10-10 Micronas Gmbh Verfahren zum Vereinzeln von in einem Körper enthaltenen elektronischen Elementen
FR2782843B1 (fr) * 1998-08-25 2000-09-29 Commissariat Energie Atomique Procede d'isolation physique de regions d'une plaque de substrat
DE10055763A1 (de) * 2000-11-10 2002-05-23 Infineon Technologies Ag Verfahren zur Herstellung einer hochtemperaturfesten Verbindung zwischen zwei Wafern
DE10158307A1 (de) * 2001-11-28 2003-02-20 Infineon Technologies Ag Verfahren zum Anschließen von Schaltungseinheiten auf Wafer-Skale-Ebene durch Dehnen einer Folie
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
TWI229435B (en) * 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
TWI227550B (en) * 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
JP4401181B2 (ja) * 2003-08-06 2010-01-20 三洋電機株式会社 半導体装置及びその製造方法
JP4018096B2 (ja) * 2004-10-05 2007-12-05 松下電器産業株式会社 半導体ウェハの分割方法、及び半導体素子の製造方法
TWI324800B (en) * 2005-12-28 2010-05-11 Sanyo Electric Co Method for manufacturing semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3260634A (en) * 1961-02-17 1966-07-12 Motorola Inc Method of etching a semiconductor wafer to provide tapered dice
FR1486041A (fr) * 1965-07-07 1967-06-23 Westinghouse Electric Corp Dispositif de protection des jonctions d'un dispositif semi-conducteur
GB1118536A (en) * 1966-09-30 1968-07-03 Standard Telephones Cables Ltd Improvements in or relating to semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2124772A1 (de) * 1970-05-21 1971-12-02 Lucas Ltd Joseph Verfahren zur Herstellung von Halb leiter Bauelementen
FR2090182A1 (enExample) * 1970-05-21 1972-01-14 Lucas Industries Ltd
FR2100997A1 (enExample) * 1970-08-04 1972-03-31 Silec Semi Conducteurs

Also Published As

Publication number Publication date
BE740836A (enExample) 1970-04-01
SE363930B (enExample) 1974-02-04
FR2021690A1 (enExample) 1970-07-24
ES373341A1 (es) 1972-05-16
GB1285708A (en) 1972-08-16
CH522955A (de) 1972-05-15
NL154868B (nl) 1977-10-17
SE376684B (enExample) 1975-06-02
FR2021690B1 (enExample) 1974-05-03
ES399979A1 (es) 1975-06-16
DK135071B (da) 1977-02-28
DE1954265A1 (de) 1970-05-27
AT310253B (de) 1973-09-25
CS168552B2 (enExample) 1976-06-29
US3756872A (en) 1973-09-04
DK135071C (enExample) 1977-08-01

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Legal Events

Date Code Title Description
NL80 Information provided on patent owner name for an already discontinued patent

Owner name: LUCAS