NL2013722B1

NL2013722B1 - Back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon and/or silicon oxide regions.

Info

Publication number: NL2013722B1
Application number: NL2013722A
Authority: NL
Inventors: Yang Guangtao; Ingenito Andrea; Zeman Miroslav; Isabella Olindo
Original assignee: Univ Delft Tech
Priority date: 2014-10-31
Filing date: 2014-10-31
Publication date: 2016-10-04
Also published as: WO2016068711A4; WO2016068711A2; WO2016068711A3

Abstract

The present invention is in the field of a process for making back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon and/or silicon oxide regions, and back side contacted solar cells. A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence "solar") , directly into electricity by the so called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.

Description

Back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon and/or silicon oxide regions

FIELD OF THE INVENTION

The present invention is in the field of a process for making back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon and/or silicon oxide regions, and back side contacted solar cells.

BACKGROUND OF THE INVENTION A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence "solar"), directly into electricity by the so-called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.

Solar cells are described as being photovoltaic irrespective of whether the source is sunlight or an artificial light. They may also be used as photo detector.

When a solar cell absorbs light it may generate either electron-hole pairs or excitons. In order to obtain an electrical current charge carriers of opposite types are separated. The separated charge carriers are "extracted" to an external circuit, typically providing a DC-current. For practi-. cal use a DC-current may be transformed into an AC-current, e.g. by using a transformer.

Typically solar cells are grouped into an array of elements. Various elements may form a panel, and various panels may form a system. A disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of 33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts were moved to a rear or back side, eliminating shaded areas. In addition thin silicon films were applied to the wafer. Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc. A qualification of performance of a solar cell is the fill factor (FF). The fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is considered to be a key parameter in evaluating performance. A typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series re-sistande and a high equivalent_shunt resistance; in other words less internal losses occur. Efficiency is nevertheless improving gradually, so every relatively small improvement is welcomed and of significant importance. A disadvantage with various prior art processes for manufacturing solar cells is that a relatively high thermal budget for manufacturing is required, which is detrimental for the solar cells and not cost effective. Such high temperature process steps are for instance used for annealing, such as annealing of silicon. For achieving high conversion efficiency solar cells, typically an additional high quality passivation layer is required in order to minimize electrical losses. Several techniques including high thermal budget (thermal Si02) or low thermal budget (ALD AI2O3 or PECVD SiN) are used. Further, as indicated above especially the efficiency of solar cells is not optimal, yet.

Some recent developments are discussed below.

The principle of oxygen-doped polycrystalline silicon (Poly-Si) is known from transistor process technology. It is also known to have doped Poly-Si (n-type or p-type). In both case, the Poly-Si layers need a thermal annealing at high temperature (T > 900 °C) . Also the (re-) crystallization of a-Si requires a (similar) high temperature thermal annealing step. I For various processes, typically additional thermally grown silicon dioxide and silicon nitride is still needed to passivate the crystalline silicon surface. The passivation layer may be an intrinsic a-Si layer, and amorphous layer, such as SiOx, and the like. Often an additional contact layer (transparent conductive oxide, TOO) is needed as well. In a way one may conclude that various process steps are not fully integrated, c.q. optimized with respect to one and another.

The present invention relates to an increased efficiency back contacted silicon based solar cell and various aspects thereof which overcomes one or more of the above disadvantages, without jeopardizing functionality and advantages.

SUMMARY OF THE INVENTION

The present invention relates in a first aspect to a silicon based solar cell with back side contacts according to claim 1, and in a second aspect to a process for making a silicon based solar cell with back side contacts according to claim 9.

The present invention makes use of various techniques in order to solve one or more of the prior art problems and provides further advantages. For instance use is made of in-situ doped microcrystalline silicon oxide or silicon layers deposited by PECVD at low temperature. It has been found that such results in a minimized surface recombination velocity and enhances lateral transport (e.g. at the front side). Such layers may be used both as passivation layer and as doped regions; it is found that these in-situ doped microcrystalline silicon oxide or silicon layers are already highly crystallized. Therefore in case of further solar cell processing a lower thermal annealing temperature (T < 900 °C) or even no annealing step is required. It has also been found that the microcrystalline silicon oxide material has an even higher band gap compared to Poly-Si; it has been found that this will make the passivated contacts more efficient in the case of carrier-selectivity. It has also been found that oxygen atoms in the above material can also effectively passivate the c-Si surface. Therefore no additional passivation layer is required.

As a result an improved silicon based solar cell is provided with an increased efficiency (10-20% relative increase) . The present process makes use of a unique combination of in-situ doped layers fabricated via epitaxy, microcrystallinity and low temperature annealing. These tech niques are preferably applied to a single-side, allowing to separately optimizing each doped region according to required specifications. The present process requires a low or reduced thermal budget (T < 900 °C) to activate dopants; it provides dopant regions which are virtually gap-less, and dopant regions that are separated by a thin dielectric layer. It has been found that the present gap-less structure reduces recombination, especially recombination occurring in case of low quality passivation layer. In addition, by reducing such gap, the overall series resistance of the device is minimized.

The above and other improvements quenches the series resistance· o'f doped regions and the leakage current between them making the shunt resistance very high leading to a high pseudo fill factor of >0.75. In a first exemplary embodiment solar cells with a conversion efficiency of 20.2 % have been fabricated; improving various aspects of the process and specifically various steps thereof a conversion efficiency of 22-23 % or more is found to be achievable. Such relates to an improvement of 1-3% over prior art devices, which is a relative improvement of 5-15%. For return of investment such a difference is considered huge.

In the present process doping techniques are single-sided. It has been found that optimizing doping profiles at a front side and back side separately minimizes overall electrical losses of a photovoltaic device. Moreover, the present gap less structure with the two doped layers separated by a trench minimizes a leakage current between two adjacent oppositely doped regions. It is noted that in an alternative approach of so-called fully implanted devices, both doped regions are fabricated via ion implantation. In such a case, a gap-less and self-aligned structure could be fabricated. However, the annealing of ion implanted boron is complicated. In particular, the activation of the boron atoms is not easy and when this is successfully achieved it requires a high thermal budget (T > 1000 °C). On the contrary, the present solution allows for in-situ doping of e.g. boron, phosphorous or arsenic, combined with phosphorous implantation in order to activate the dopants at low temperature (T < 900 °C, typically < 800 °C). Such annealing advantageously occurs during the growth of the epitaxial layer; hence no extra annealing step is required.

With respect to prior art solar cells fabricated via diffusion, the present invention involves the use of doping techniques which can either accurately provide a required doping profile or overcome technical limitations of a diffusion process. In fact, in case of standard doping diffusion, the doping profile is found to be limited by the solid solubility of the dopants in silicon, hence can not be optimized fully. The combination of e.g. ion implanted phosphorous and epitaxial .grown of Si doped in situ with e.g. boron enables the use of a low temperature annealing step (see e.g. fig. 2). In addition, by using single-side doping techniques, the doping profile of each doped layer can be separately optimized. A disadvantage the present invention is that an additional doping is required with respect to a prior art process and that epitaxial growth is not yet a mainstream technique in PV industry.

In an example the solar cells are so-called Interdigitated Back Contact (IBC) solar cell structures.

Thereby the present invention provides a solution to one or more of the above mentioned problems.

Advantages of the present description are detailed throughout the description. References to the figures are not limiting, and are only intended to guide the person skilled in the art through details of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates in a first aspect to a reduced temperature process for interdigitated back contacted solar cells according to claim 1. It is noted that in principle n-doped regions and p-doped regions may be interchanged. If an in-situ doped epitaxial layer is n-doped a back surface field is formed, if it is p-doped an emitter is formed. Dopant concentrations are in the order of 1*1017/cm3-l*1019/cm3.

In an example the present solar cell is double sided polished (fig. la). In a further example the solar cell is one side polished and one side textured, and in a further example it is double sided textured (fig lb). A textured surface increases surface recombination. In this respect it has been found that a textured surface preferably has an aspect ratio (height: depth of a textured structure) of 2-10, preferably 5-8.

In an example of the present solar cell the doped regions are formed by PECVD and thermal annealing thereafter .

In an example of the present solar cell the contacts independently consist of in-situ doped semi-insulating material, such as micro-crystalline thin-film silicon'and micro-crystalline thin film silicon oxide. It has been found that’ such contacts minimize contact recombination of both silicon and silicon/metal surfaces; hence increase efficiency.

In an example of the present solar cell the contacts are passivated. Such is found to reduce contact recombination and reduces the number of process steps.

In an example of the present solar cell the undoped silicon-oxide tunneling layer between the n-doped or p-doped regions is present only between doped regions and the silicon substrate. The tunneling layer is preferably an un-doped Si02 layer, having a thickness of less than 3 nm, preferably less than 2 nm, such as less than 1.5 nm.

In an example of the present solar cell further comprises an un-doped silicon oxide on a front side of the silicon substrate, a doped layer on said front side silicon oxide layer, and a passivation layer on said doped front side layer. Thereby a front side field is further optimized .

In an example of the present solar cell the oppositely doped regions are separated by trenches, wherein trenches are filled with a (semi) insulating material. Therewith the above mentioned advantages are achieved.

In an example of the present solar cell the microcrystalline thin-film silicon and micro-crystalline thin film silicon oxide each independently comprise hydrogen in a concentration of 0.2-20 atom%. It has been found that hy- drogen improves passivation characteristics of the thin-f ilm.

In an example the present solar cell or light detector has an efficiency of > 21%, a series resistance of < 1 Ohm*cm, a shunt resistance of > 1000 Ohm*cm, a fill factor of > 75%, a pitch of 0.1-5 mm, wherein the epitaxial-doped region and ion-implant-doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region, a leakage current of < 1000 fA/cm2. It preferably has a front side aspect ratio of >50.

In an example the present device has a different FSF and BSF.

In a second aspect the present invention relates to a process for manufacturing a solar cell according to the invention, comprising the steps of providing a silicon substrate, providing at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from thin-film silicon and thin film silicon oxide, annealing said doped regions at a temperature of less than 900 °C during a sufficient period of time, providing an un-doped silicon-oxide tunneling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and providing contacts each being in electrical contact with a doped region. It is noted that the present process has a disadvantage, namely a somewhat more complicated process flow for the fabrication of the photovoltaic device.

In an example of the present process a first doped layer is etched, thereby forming first doped regions, and thereafter second doped regions are formed, preferably wherein first and second doped regions are alternating.

In an example of the present process after forming a second doped layer, both doped layers are covered with an insulating layer, the insulating layer extending in between oppositely doped regions.

In an example of the present process doped regions are deposited by low temperature PECVD.

In an example of the present process contacts are provided by metal deposition and lift off (of non-contact areas), screen printing, and electrical plating. As such the photovoltaic energy can be harvested. Metal may be deposited using sputtering techniques. It is preferred to use copper, aluminum, or tungsten as metal. In an alternative, after deposition, the non-contact areas can be etched in order to remove the metal.

In an example of the present process an area of a p-doped region is two- to eight- times an area of an n-doped region.

In an example of the present process the n-doped region and p-doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region.

As -is detailed above such provides for improved characteristics of the present solar cell.

In an example the present process further comprises forming a doped region at the front side of the wafer, thereby forming a front doped region, wherein the front doped region is independently selected from the back side doped region (see fig. 6). The front doped region may form a front side field (FSF). By independently doping a front and a back side especially the fill factor of the solar cell can be improved.

In an example the present process further comprises the step of an anti-reflective coating the solar cell. Such an anti-reflective coating improves light absorbance, and reduces recombination.

In an example of the present process p-doped regions and n-doped regions have a pitch of 0.1 mm-5 mm, such as of 1-2 mm. The pitch is used to describe a distance between repeated elements in a structure possessing translational symmetry: in the present case, a sequence of alternating p-doped regions and n-doped regions. It has been found that by optimizing the pitch also characteristics of the solar cell can be optimized.

In an example of the present process at least one side of the wafer is provided with a texture, such as a microscale texture, a nanoscale texture, and combinations thereof,· wherein the texture preferably has a high aspect ratio. The aspect ratio is preferably 2-10, preferably 5-8.

It has been found that a high aspect ratio improves energy conversion .

In an example of the present process the back side doped region and the front side doped region are different.

In an example the front side doped region has a dopant concentration of l*1017/cm3-l*1019/cm3, whereas the back side doped region a relative dopant concentration of >105% of the front side doped region.

The invention is further detailed by the accompanying figures and examples, which are exemplary and explanatory of nature and are not limiting the scope of .the inven- · tion. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims.

SUMMARY OF FIGURES

Figures 1-10 show a schematic representation of an example of the present process. DETAILED DESCRIPTION OF FIGURES 21: Si wafer 31: intrinsic SiOx tunneling layer 32: intrinsic SiOx protective layer 41: n-doped layer 42: p-doped layer 45: front side field 51: SiN layer 61: Photo-resist 71: metal

The figures are further detailed in the description of the experiments below.

In figure 1 a silicon wafer is provided. The wafer is cleaned using 99% wt. % HN03. During 10 min. of cleaning the temperature is increased to 110 °C. If the wafer is textured 6-8 wt. % HN03 is used. A textured wafer is than obtained (fig 10), which textured wafer may be processed in a similar fash- ^ ion as a non-textured wafer. On the bottom side of the wafer a 1 nm intrinsic SiOx tunneling layer 31 is formed by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HN03 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the concentration of HNO3 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from Ι-ΒΟ min. Thereafter a first in-situ doped layer 41 of 20 nm is made by PECVD. A B-dopant concentration reached is 1019/cm3. As an alternative to B P may be used, than changing the dopant type from p to n.

The thickness of the layer may be from 10-100nm. A temperature used during PECVD is from 100-300 °C. Typically gases used are SiH4 (or SiF4) , C02, B2H6 (for p-type material, or PH3 for n-type material), and optionally H2.

After deposition of the n- or p-type doped layer a protective layer 32 is deposited, such as a SiOx or SiNx protective layer. A layer thickness used is 80 nm, which may vary from 10-100 nm. Typically a PECVD system is used for deposition, using a temperature between 100 and 300 °C, such as 150 °C. Typical gases used are SiH4 (or S1F4) , H2, and C02 for SiOx, or SiH4 (or SiF4) , H2, and NH3 for SiNx material.

In Fig. 2 a photoresist is applied. A pattern is formed, defining first doped regions. Thereto a 248 nm light source is used. The protective layer, first doped layer, and tunneling layer are isotropically etched using dry etching.

In fig. 3 conformal layers are deposited. First an intrinsic SiOx tunneling layer 31 is formed by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HN03 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the concentration of HN03 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min. Thereafter a second in-situ doped layer 42 of 20 nm is made by PECVD. A P-dopant concentration reached is 1019/cm3. As an alternative to P B may be used, than changing the dopant type from n to p.

The thickness of the layer may be from 10-100 nm. A temperature used during PECVD is from 100-300 °C. Typically gases used are S1H4 (or SiF4) , C02, PH3 (for p-type material, or B2H5 for n-type material), and optionally H2. Thereafter a protective layer 32 is deposited, such as a SiOx or SiNx protective layer. A layer thickness used is 80 nm, which may vary from 10-100 nm. Typically a PECVD system is used for deposition, using a temperature between 100 and 300 °C, such as 150 °C. Typical gases used are SiH4 (or SiF4) , H2, and CO2 for SiOx, or SiH4 (or SiF4) , H2, and NH3 for SiNx material.

In fig. 4 a photoresist 61 is applied. A pattern is formed, defining second doped regions. Thereto a 248 nm light source is used.

In fig. 5 the protective layer, first doped layer, and tunneling layer are etched using wet etching, such as using 10% HF. The first and second doped regions are in the example alternating. The regions are separated by a (later added) dielectric material.

In fig. 6 -a 1 nm intrinsic SiOx tunneling layer 31 is formed on the front side of the wafer by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HN03 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the concentration of HN03 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min. Next a front side field (FSF) layer 45 of 20 nm is formed. The P-dopant concentration is 5 1018/cm3. A typical equipment used is a PECVD system using a temperature between 100 and 300 °C, such as 150 °C. Typical gases used are SiH4, C02, PH3, and H2. Thereafter the processed wafer is annealed, at temperature less than 1000 °C, typically less than 900°C, in N2, for a proper duration. A process time is from 10-60 min., such as 30 minutes. After annealing an anti-reflective coating (ARC) 51 of 10-100 nm, such as 80 nm, is provided. Typically a PECVD system is used for deposition, using a temperature between 100 and 300 °C, such as 150 °C. Typical gases used are SiH4 (or SiF4) , optionally H2, and NH3 for SiNx material. At the bottom side a similar layer 51 is deposited as well, the layer extending in between the doped regions, thereby electrically separating these doped regions from one and another.

In fig. 7 a photoresist 61 is applied. A pattern is formed, defining contact areas on the doped layers. Thereto a 248 nm light source is used and the photoresist is partially etched.

In fig. 8 the layers 51 and 31 are etched up to the first and second doped layer, respectively

In fig. 9 a 2 μπι metal layer 71 is deposited using PVD, such as an Al-layer. The metal layer may be from 0.2-5 pm. For non-contact regions the metal is lift-off. As an alternative a metallization process can be replaced by a screen-printing process.

In fig. 10 a textured wafer is shown, in this case textured at both sides thereof.

EXAMPLES/EXPERIMENTS

The invention although described in detailed explanatory context may be best understood in conjunction with the accompanying figures.

It should be appreciated that for commercial application it may be preferable to use one or more variations of the present system, which would similar be to the ones disclosed in the present application and are within the spirit of the invention.

For the purpose of searching prior art the following section is added, representing a translation of the claims in English : 1. Increased efficiency silicon based solar cell with back side contacts, comprising a silicon substrate, at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from micro-crystalline thin-film silicon and micro-crystalline thin film silicon oxide, an un-doped silicon-oxide tunnelling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and wherein each contact is in electrical contact with a doped region. 2. Solar cell according to claim 1, wherein the solar cell is double sided polished, one side polished and one side textured, or double sided textured. 3. Solar cell according to any of the preceding claims, wherein the doped regions are formed by PECVD and thermal annealing thereafter. 4. Solar cell according to any of the preceding claims, wherein the contacts independently consist of in-situ doped semi-insulating material, such as micro-crystalline thin-film silicon and micro-crystalline thin film silicon oxide. 5. Solar cell according to any of the preceding claims, wherein the contacts are passivated. 6. Solar cell according to any of the preceding claims, wherein the un-doped silicon-oxide tunnelling layer between the n-doped or p-doped regions is present only between doped regions and the silicon substrate. 7. Solar cell according to any of the preceding claims, further comprising an un-doped silicon oxide on a front side of the silicon substrate, a doped layer on said front side silicon oxide layer, and a passivation layer on said doped front side layer. 8. Solar cell according to any of the preceding claims, wherein the oppositely doped regions are separated by trenches, wherein trenches are filled with a (semi) insulating material. 9. Solar cell according to any of the preceding claims, wherein the micro-crystalline thin-film silicon and microcrystalline thin film silicon oxide each independently comprise hydrogen in a concentration of 0.2-20 atom%. 10. Process for manufacturing a solar cell according to any of claims 1-9, comprising the steps of providing a silicon substrate, providing at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from thin-film silicon and thin film silicon oxide, annealing said doped regions at a temperature of less than 900 °C during a sufficient period of time, providing an un-doped silicon-oxide tunnelling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and providing contacts each being in electrical contact with a doped region. 11. Process according to claims 10, wherein a first doped layer is etched, thereby forming first doped regions, and thereafter second doped regions are formed, preferably wherein first and second doped regions are alternating. 12. Process according to any of claims 10-11, wherein after forming a second doped layer, both doped layers are covered with an insulating layer, the insulating layer extending in between oppositely doped regions. 13. Process according to any of claims 10-12, wherein doped regions are deposited by low temperature PECVD. 14. Process according to any of the preceding claims, wherein contacts are provided by metal deposition and lift off (of non-contact are.as) , screen printing, and electrical plating.

Claims

An increased efficiency silicon-based solar cell with reverse contacts, comprising a silicon substrate, at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from microcrystalline silicon thin film and microcrystalline thin film silicon oxide, a non-doped silicon oxide tunneling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and wherein each contact is in electrical contact with a doped region.

Solar cell according to claim 1, wherein the solar cell is polished on both sides, polished on one side and structured on one side, or structured on both sides.

A solar cell according to any one of the preceding claims, wherein the doped regions are formed by PECVD and then thermally annealed.

A solar cell according to any one of the preceding claims, wherein the contacts are independently of in situ doped semi-insulating material, such as microcrystalline thin-film silicon and microcrystalline thin-film silicon oxide.

Solar cell according to one of the preceding claims, wherein the contacts are passivated.

The solar cell according to any one of the preceding claims, wherein the undoped silicon oxide tunneling layer between the n-doped or p-doped regions is only present between doped regions and the silicon substrate.

The solar cell according to any of the preceding claims, further comprising an undoped silicon oxide on a front side of the silicon substrate, a doped layer on the silicon oxide front layer, and a passivation layer on the front-doped layer.

A solar cell according to any one of the preceding claims, wherein the oppositely doped regions are separated by slots, wherein slots are filled with a (semi) insulating material.

The solar cell according to any one of the preceding claims, wherein the microcrystalline thin film silicon and microcrystalline thin film silicon oxide each independently contain hydrogen in a concentration of 0.2-20 atomic%.

A method for manufacturing a solar cell according to any of claims 1-9, comprising the steps of providing a silicon substrate, providing at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from thin film silicon thin film and silicon oxide, annealing the doped regions at a temperature of less than 900 ° C for a sufficiently long period, providing an undoped silicon oxide tunneling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and providing contacts that are each in electrical contact with a doped region.

The method of claim 10, wherein a first doped layer is etched, thereby forming first doped regions, and then second doped regions are formed, preferably wherein first and second doped regions are alternated.

The method of any one of claims 10-11, wherein after forming a second doped layer, both doped layers are covered with an insulating layer, the insulating layer extending between oppositely doped regions.

The method of any one of claims 10-12, wherein doped regions are deposited by low temperature PECVD.

A method according to any one of the preceding claims, wherein contacts are provided by metal deposition and cancellation (of contactless areas), by screen printing, and by electrically plating.