KR20180045587A - Solar cell and meaufacturing method of solar cell - Google Patents

Abstract

The present invention relates to a solar cell and a manufacturing method thereof. The solar cell includes a substrate (110,210,310) composed of a semiconductor, a charge selective emitter layer (130,230,330) formed on the front surface of the substrate (110,210,310), and a charge selective electric field layer (120,220,320) formed on the rear side of the substrate (110,210,320). The present invention can increase efficiency and reduce a loss of the solar cell by preventing carrier recombination by forming the charge selective emitter layer on the front surface of an n-type crystalline silicon substrate and the charge selective electric field layer on the rear surface of the n-type crystalline silicon substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a solar cell,

The present invention relates to a solar cell and a method of manufacturing the same, and more particularly, to a solar cell having a structure capable of reducing recombination in a single junction solar cell and a method of manufacturing the same.

Solar cells are devices that convert light energy into electrical energy through photoelectric energy conversion.

The efficiency of a single junction solar cell composed of p-n junctions is around 30% under ideal conditions and involves optical and electrical losses. One of the main electrical losses of a single junction solar cell composed of a p-n junction is recombination, and particularly the loss at the interface between the silicon substrate, the doping layer, and the electrode is large.

1, an energy band diagram of a p-n junction solar cell is shown.

As shown in FIG. 1, the pn junction solar cell has an n + emitter layer, a p-type silicon substrate, and a p + whole layer (BSF) structure. In the pn junction, electrons and holes are offset from each other, A depletion layer is formed, and a potential difference (diffusion potential) is generated at both ends of the depletion layer. In order to harmonize with this potential difference, carrier recombination occurs inside.

Carriers generated by light absorption are separated and moved to the surface of both ends of the cell to form a voltage. Therefore, in order to generate a high voltage, separated carriers must be accumulated without being recombined. Here, the carrier means electrons and holes.

In order to solve this problem, as shown in FIG. 2, the rear front layer 20 of the silicon substrate 10 is formed as a charge selective front layer of a thin film of SiO ₂ 21 and n + doped polysilicon 23, However, since the front emitter layer 30 is formed by the doping method, the front carrier recombination problem occurs as shown in FIG.

Patent Document 1: Korean Patent Publication No. 2012-0085067 (published on July 31, 2012)

It is an object of the present invention to provide a solar cell having a structure capable of remarkably reducing carrier recombination on the front and back surfaces of a semiconductor substrate in a single junction solar cell and a manufacturing method thereof .

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a charge selective emitter layer formed on a front surface of the substrate; and a charge selectable front layer formed on a rear surface of the substrate.

The substrate is an n-type silicon substrate.

The charge selection type emitter layer is a stacked structure of SiO ₂ and p + -doped polysilicon thin film, and the charge selection type whole layer is a stacked structure of SiO ₂ and n + doped polysilicon thin film.

The charge selective emitter layer is a heterojunction emitter, and the charge selection type whole layer is a stacked structure of SiO ₂ and n + doped polysilicon thin films.

The heterojunction emitter is a P-type material having a wide bandgap.

The charge selection type emitter layer is a transition metal oxide having a higher work function than silicon, and the charge selection type whole layer is a stacked structure of SiO ₂ and n + doped polysilicon thin films.

The transition metal oxides include _{V 2 O X, M O O} X.

A transparent electrode for compensating electrical conductivity is deposited on the transition metal oxide.

The transparent electrode is ITO or ZnO.

Comprising the steps of: preparing a substrate made of a semiconductor; forming a charge selective emitter layer on the front surface of the substrate; and forming a charge selective front layer on the rear surface of the substrate.

The substrate is an n-type silicon substrate.

Forming a charge optional emitter layer on the front surface of the substrate, the heat-treated, a wet process, sputtering, CVD method, the method of any one of SiO ₂ on the entire surface of the substrate And the step of growing a thin SiO ₂ And laminating a p + doped polysilicon thin film on top of the thin film.

The step of forming the charge selective emitter layer on the entire surface of the substrate may be performed by any one of sputtering and CVD methods selected from among hydrogenated amorphous silicon, doped microcrystalline silicon compound, and doped microcrystalline silicon- On the entire surface of the substrate.

Forming a charge optional emitter layer on the front surface of the substrate, the transition metal oxide of one kind selected from V ₂ O _X, M _O O _X by the evaporation method, the method of any one of sputter depositing on the entire surface of the substrate .

And laminating a transparent electrode for compensating electrical conductivity on the transition metal oxide.

The transparent electrode is ITO or ZnO.

Forming a charge optional layer around the back of the substrate, the heat-treated, a wet process, sputtering, CVD method, the method of any one of SiO ₂ on the rear surface of the substrate Growing a thin film; And the SiO ₂ And depositing n + doped amorphous silicon or microcrystalline silicon thin film on the bottom of the thin film.

Doping the n + doped amorphous silicon or microcrystalline silicon thin film, and then heat treating the substrate at a temperature of 600 ° C or higher to induce recrystallization of the n + doped amorphous silicon or microcrystalline silicon thin film.

The step of forming the charge selective emitter layer and the step of forming the charge selection type whole layer further include the step of hydrogen plasma treatment for surface recombination reduction.

The present invention has the effect of reducing loss of a solar cell and improving efficiency by forming a charge selective emitter layer on the entire surface of an n-type crystalline silicon substrate and forming a charge selectable front layer on the rear surface of the n-type crystalline silicon substrate .

1 is an energy band diagram of a pn junction solar cell.
2 is a cross-sectional view showing a conventional solar cell structure.
Figure 3 is an energy band diagram of the solar cell structure of Figure 2;
4 illustrates a solar cell structure according to an embodiment of the present invention.
Figure 5 is an energy band diagram of the solar cell structure of Figure 4;
6 is a view showing a structure of a solar cell according to another embodiment of the present invention.
Figure 7 is an energy band diagram of the solar cell structure of Figure 6;
8 is a view showing a structure of a solar cell according to another embodiment of the present invention.
Figure 9 is an energy band diagram of the solar cell structure of Figure 8;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The solar cell of the present invention includes a substrate made of a semiconductor, a charge selective emitter layer formed on the front surface of the substrate, and a charge selectable front layer formed on the rear surface of the substrate.

The substrate is an n-type crystalline silicon substrate. Both the front emitter layer and the backside layer (BSF) of the substrate employ charge-selective bonding to prevent carrier recombination on the front and back sides.

A method of forming a front emitter layer and a back front layer on an n-type crystalline silicon substrate is described in three embodiments.

[Example]

FIG. 4 illustrates a solar cell structure according to an embodiment of the present invention, and FIG. 5 illustrates an energy band diagram of the solar cell structure of FIG.

4, the solar cell includes an n-type crystalline silicon substrate 110, a charge selection type front layer 120 formed on the rear surface of the substrate 110, a charge selection type emitter layer 110 formed on the front surface of the substrate 110, (130).

The charge selection type whole layer 120 is a stacked structure of SiO ₂ and n + doped polysilicon thin films 121 and 123.

The charge selection type emitter layer 130 is a stacked structure of SiO ₂ and p + -doped polysilicon thin films 131 and 133.

A method of manufacturing a solar cell according to an embodiment includes preparing an n-type crystalline silicon substrate 110, forming a charge selective front layer 120 on a rear surface of the substrate 110, And forming a selective emitter layer (130).

The step of forming the charge selective front layer 120 on the rear surface of the substrate 110 and the step of forming the charge selective emitter layer 130 on the front surface of the substrate 110 may be performed simultaneously or sequentially .

Forming a charge before optional layer 120, heat treatment, to the back of the wet process, sputtering, CVD method to any one of the method the substrate 110 of SiO ₂ The thin film 121 is grown, and SiO ₂ An n + doped polysilicon thin film 121 is laminated on the lower portion of the thin film 121. [

Forming a charge optional emitter layer 130, the entire surface of the SiO ₂ of the heat treatment, a wet process, sputtering, CVD method to any one of the method the substrate 110 of the The thin film 131 is grown, and SiO ₂ Doped polysilicon thin film 133 is formed on the thin film 131 by stacking.

polysilicon thin film (123 133) doped with p + and n + SiO ₂ is formed on the front and back of the substrate 110 from the substrate 110 temperature less than 600 ℃ Amorphous silicon may be laminated on the thin films 121 and 131 and then recrystallized or directly laminated with microcrystalline silicon.

After the rear amorphous silicon or microcrystalline silicon is deposited, the substrate 110 may be heat-treated at a temperature of 600 ° C or higher to induce recrystallization with the doped polysilicon thin films 123 and 133. Through recrystallization, the amorphous silicon recrystallizes into polysilicon and can function as a rear field thin film.

The solar cell of one embodiment can be hydrogen plasma treated after manufacture. The hydrogen plasma treatment induces a chemical passivating effect that combines with the dangling bond of the silicon surface to reduce surface recombination.

As shown in Fig. 5, the solar cell of one embodiment has SiO ₂ The thin film serves as an insulating film to prevent carrier recombination.

To move electrons from the substrate at Ec (conduction band) into the emitter layer and the holes in the (valence band) Ev moving the substrate in the emitter layer SiO ₂ The thin film is prevented and the separated carriers are not recombined.

[Other Embodiments]

FIG. 6 shows a solar cell structure according to another embodiment of the present invention, and FIG. 7 shows an energy band diagram of the solar cell structure of FIG.

6, the solar cell includes an n-type crystalline silicon substrate 210, a charge selection type front layer 220 formed on the rear surface of the substrate 210, a charge selection type emitter layer 220 formed on the entire surface of the substrate 210, (230).

The charge select type whole layer 220 is a stacked structure of SiO ₂ and n + doped polysilicon thin films 221 and 223.

The charge select emitter layer 230 is a heterojunction emitter.

The heterojunction emitter is a P-type material having a band gap (Eg) larger than that of the substrate 210. The bandgap means the gap between Ec and Ev. The wide band gap makes it difficult to transfer electrons from Ec to Ev to prevent carrier recombination.

The method of manufacturing a solar cell according to another embodiment includes the steps of preparing an n-type crystalline silicon substrate 210, forming a charge selective front layer 220 on the rear surface of the substrate 210, And forming a charge selective emitter layer (230).

The step of forming the charge selective front layer 220 on the rear surface of the substrate 210 and the step of forming the charge selective emitter layer 230 on the front surface of the substrate 210 may be performed simultaneously or sequentially .

Forming a charge before optional layer 220, heat treatment, to the back of the substrate 210 by the method of any one of wet processes, sputtering, CVD method SiO ₂ And growing a thin film 221, the SiO ₂ figures And an n + doped polysilicon thin film 221 is laminated on the lower portion of the thin film 221.

n + doped polysilicon thin film 221 is a SiO ₂ formed on the front and back of the substrate 210 at a temperature below 600 ℃ substrate 210 The amorphous silicon may be deposited on the thin film 221 and then recrystallized or directly stacked with microcrystalline silicon.

After the rear amorphous silicon or microcrystalline is deposited, the substrate 210 may be heat-treated at a temperature of 600 ° C or higher to induce recrystallization of the n + doped polysilicon thin film 221. Through recrystallization, the amorphous silicon recrystallizes into polysilicon and can function as a rear field thin film.

The step of forming the charge selection type emitter layer 230 may include forming at least one selected from hydrogenated amorphous silicon, doped microcrystalline silicon compound, and doped microcrystalline silicon-carbon alloy by sputtering or CVD (210).

The charge selection type emitter layer 230 can make the above-described multiple materials into a laminated structure.

In the solar cell of another embodiment, as shown in Fig. 7, a wide band gap Eg at the p-n junction prevents carrier recombination at the interface.

[Another Embodiment]

FIG. 8 shows a solar cell structure according to another embodiment of the present invention, and FIG. 9 shows an energy band diagram of the solar cell structure of FIG.

8, the solar cell includes an n-type crystalline silicon substrate 310, a charge selection type front layer 320 formed on the rear surface of the substrate 310, a charge selection type emitter layer 310 formed on the front surface of the substrate 310, (330).

The charge selection type whole layer 320 is a stacked structure of SiO ₂ and n + doped polysilicon thin films 321 and 323.

The charge selective emitter layer is a transition metal oxide with a high work function. Transition metal oxides include _{V 2 O X, M O O} X. When the work function of the substrate is sufficiently higher than that of the emitter layer, the holes are recombined at the interface of the emitter layer, but another hole is generated in the emitter layer to preserve the charge.

Transparent electrodes can be deposited on top of the transition metal oxide to compensate for the low electrical conductivity of the transition metal oxide. The transparent electrode may be ITO or ZnO.

The method of manufacturing a solar cell according to another embodiment includes the steps of preparing an n-type crystalline silicon substrate 310, forming a charge selective front layer 320 on the rear surface of the substrate 310, To form a charge selective emitter layer (330).

The step of forming the charge selective front layer 320 on the rear surface of the substrate 310 and the step of forming the charge selective emitter layer 330 on the front surface of the substrate 310 may be performed simultaneously or sequentially .

Forming a charge before optional layer 320, heat treatment, to the back of the substrate 310 by the method of any one of wet processes, sputtering, CVD method SiO ₂ And growing a thin film 321, the SiO ₂ figures An n + doped polysilicon thin film 321 is formed on the lower surface of the thin film 321 by lamination.

n + doped polysilicon thin film 321 is a SiO ₂ formed on the front and back of the substrate 310 at a temperature below 600 ℃ substrate 310 The amorphous silicon may be laminated on the thin film 321 and then recrystallized or directly laminated with microcrystalline silicon.

After the rear amorphous silicon or microcrystalline silicon is laminated, the substrate 310 may be heat-treated at a temperature of 600 ° C or higher to induce recrystallization with the n + doped polysilicon thin film 321. Through recrystallization, the amorphous silicon recrystallizes into polysilicon and can function as a rear field thin film.

The step of forming the charge selection type emitter layer is formed by depositing one kind of transition metal oxide selected from V ₂ O _x and M _O O _{x on the} entire surface of the substrate by any one of evaporation method and sputtering method.

Next, a transparent electrode for compensating electrical conductivity can be laminated on the transition metal oxide. The transparent electrode may be ITO or ZnO.

The solar cell of another embodiment recombines electrons and holes at the interface of the wafer and the transition metal oxide emitter layer, as shown in Fig. 9, and another hole is generated inside the emitter layer to preserve the charge.

As described above, the charge selective emitter layers 130, 230, and 330 are formed on the entire surface of the n-type crystalline silicon substrate 110, 210, and 310, and the charge selection type front layers 120, 220 and 320 are formed on the rear surface.

The charge selection type emitter layers 130, 230 and 330 are formed of a laminated structure of SiO ₂ and p + doped polysilicon thin film. SiO ₂ Function as an insulating film to prevent carrier recombination.

Alternatively, the charge selective emitter layer is formed by a heterojunction emitter. This forms a laminated structure including a p + semiconductor having a wide band gap to prevent carrier recombination.

Alternatively, the charge selective emitter layer is formed of a transition metal oxide. When the work function of the substrate is sufficiently higher than that of the emitter layer, the holes are recombined at the interface of the emitter layer, but another hole is generated in the emitter layer to preserve the charge.

The whole layer of the charge selection type is formed by a lamination structure of SiO ₂ and n + doped polysilicon thin film. Further, after the formation of the laminated structure of the SiO ₂ and the n + doped polysilicon thin film, the hydrogen recombination is reduced by hydrogen bonding to the dangling bonds at the interface through the hydrogen plasma treatment.

Best Mode for Carrying Out the Invention The present invention has been described with reference to the drawings and the specification. Although specific terms are used herein, they are used for the purpose of describing the present invention only and are not used to limit the scope of the present invention described in the meaning of the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

110, 210, 310: Substrate 120, 220, 320:
130, 230, 330: Charge Selective Emitter Layer

Claims (19)

A substrate made of a semiconductor;
A charge selective emitter layer formed on the front surface of the substrate; And
And a charge selectable front layer formed on a rear surface of the substrate. The method according to claim 1,
Wherein the substrate is an n-type silicon substrate. The method of claim 2,
The charge selection type emitter layer is a stacked structure of SiO ₂ and a p + -doped polysilicon thin film,
Wherein the charge selection type whole layer is a stacked structure of SiO ₂ and an n + doped polysilicon thin film. The method of claim 2,
Wherein the charge selective emitter layer is a heterojunction emitter,
Wherein the charge selection type whole layer is a stacked structure of SiO ₂ and an n + doped polysilicon thin film. The method of claim 4,
Wherein the heterojunction emitter is a P-type material and has a band gap (Eg) larger than that of the substrate. The method of claim 2,
Wherein the charge selective emitter layer is a transition metal oxide having a higher work function than silicon,
Wherein the charge selection type whole layer is a stacked structure of SiO ₂ and an n + doped polysilicon thin film. The method of claim 6,
Wherein the transition metal oxide comprises V ₂ O _X , M _O O _X. The method of claim 7,
And a transparent electrode for compensating electrical conductivity is stacked on top of the transition metal oxide. The method of claim 8,
Wherein the transparent electrode is ITO or ZnO. Preparing a substrate made of a semiconductor;
Forming a charge selective emitter layer on a front surface of the substrate; And
And forming a charge selective front layer on the rear surface of the substrate. The method of claim 10,
Wherein the substrate is an n-type silicon substrate. The method of claim 11,
Forming a charge selective emitter layer on the front surface of the substrate,
Growing a SiO ₂ thin film on the entire surface of the substrate by any one of heat treatment, wet process, sputter, and CVD; And
The SiO ₂ And laminating a p + doped polysilicon thin film on top of the thin film. The method of claim 11,
Forming a charge selective emitter layer on the front surface of the substrate,
And growing at least one selected from hydrogenated amorphous silicon, doped microcrystalline silicon compound and doped microcrystalline silicon-carbon alloy on the entire surface of the substrate by any one of a sputtering method and a CVD method Gt; The method of claim 11,
Forming a charge selective emitter layer on the front surface of the substrate,
A transition metal oxide of one kind selected from _{V 2 O X, M O O} X by the evaporation method, the method of any one of a sputtering method for producing a solar cell comprising the step of laminating the entire surface of the substrate. 15. The method of claim 14,
And laminating a transparent electrode for compensating electrical conductivity on the transition metal oxide. 15. The method of claim 14,
Wherein the transparent electrode is made of ITO or ZnO. The method of claim 11,
Forming a charge selective front layer on a backside of the substrate,
Growing a SiO ₂ thin film on the rear surface of the substrate by any one of a heat treatment, a wet process, a sputtering process, and a CVD process; And
The SiO ₂ And laminating an n + doped polysilicon thin film on the bottom of the thin film. 18. The method of claim 17,
The step of laminating the n + doped polysilicon thin film comprises:
The SiO ₂ After the step of laminating amorphous silicon or microcrystalline silicon thin film on the bottom of the thin film,
And annealing the amorphous silicon or microcrystalline silicon thin film to an n + doped polysilicon thin film by performing heat treatment at a temperature of 600 ° C or higher of the substrate. The method of claim 11,
Further comprising the step of: performing hydrogen plasma treatment to reduce the surface recombination after the step of forming the charge selective emitter layer and the step of forming the charge selection type whole layer.

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