NL2018491B1 - Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells - Google Patents
Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells Download PDFInfo
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- NL2018491B1 NL2018491B1 NL2018491A NL2018491A NL2018491B1 NL 2018491 B1 NL2018491 B1 NL 2018491B1 NL 2018491 A NL2018491 A NL 2018491A NL 2018491 A NL2018491 A NL 2018491A NL 2018491 B1 NL2018491 B1 NL 2018491B1
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- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 13
- 238000000059 patterning Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 10
- 239000010703 silicon Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000000151 deposition Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 239000001257 hydrogen Substances 0.000 claims description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 10
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 7
- 239000002243 precursor Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 240000004760 Pimpinella anisum Species 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 claims 1
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- BDVZHDCXCXJPSO-UHFFFAOYSA-N indium(3+) oxygen(2-) titanium(4+) Chemical compound [O-2].[Ti+4].[In+3] BDVZHDCXCXJPSO-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The present invention is in the field of a method for mask-less patterning of amorphous silicon layers, such as for low-cost silicon hetero-junction interdigitated back-contact solar cells, solar-cells and PV-panels obtainable by said method, in particular Silicon-Heterojunction (SHJ) interdigitated back- contacted (IBC) solar cells.
Description
FIELD OF THE INVENTION
The present invention is in the field of a method for mask-less patterning of amorphous silicon layers, such as for low-cost silicon hetero-junction interdigitated back-contact solar cells, solar-cells and PV-panels obtainable by said method, in particular Silicon-Heterojunction (SHJ) interdigitated back-contacted (IBC) solar cells.
BACKGROUND OF THE INVENTION
A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence solar), directly into electricity by the socalled photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.
Solar cells are described as being photovoltaic irrespective of whether the source is sunlight or an artificial light. They may also be used as photo detector.
When a solar cell absorbs light it may generate either electron-hole pairs or excitons. In order to obtain an electrical current charge carriers of opposite types are separated. The separated charge carriers are extracted to an external circuit, typically providing a DC-current. For practical use a DC-current may be transformed into an AC-current, e.g. by using a transformer.
Typically solar cells are grouped into an array of elements. Various elements may form a panel, and various panels may form a system.
A disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of 33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts were moved to a rear or back side, eliminating shaded areas. In addition thin silicon films were applied to the wafer. Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc. A qualification of performance of a solar cell is the fill factor (FF). The fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is considered to be a key parameter in evaluating performance. A typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt resistance; in other words less internal losses occur. Efficiency is nevertheless improving gradually, so every relatively small improvement is welcomed and of significant importance.
A disadvantage with various prior art processes for manufacturing solar cells is that a relatively high number of mask-steps is required for manufacturing, which is not cost effective .
The present invention therefore relates to an improved method for mask-less patterning of amorphous silicon layers, which solve one or more of the above problems and drawbacks of the prior art, providing reliable results, without jeopardizing functionality and advantages.
SUMMARY OF THE INVENTION
It is an object of the invention to overcome one or more limitations of the methods and devices of the prior art and at the very least to provide an alternative thereto.
In a first aspect, the invention relates to a method of mask-less patterning of an amorphous silicon layer according to claim 1. Therein a Si<100> oriented substrate 11 is provided. The substrate thickness is typically in a range of 100 pm-20 mm, such as 150 pm-l mm. For solar cells typically
Si-wafers may be used, having a thickness of 150 μπι-300 gm. The substrate is textured on at least one side thereof, preferably on a back side, such as by anisotropic etching. Thereby <111> surfaces are formed, typically in a zig-zag like pattern (in cross-sectional view). Part of the surface is not textured, typically an edge-part thereof. The non-textured surface remains a <100> surface. The <100> surface area is typically about 2-50% of the full surface area, such as 15-20% (hence 50-98% <111> surface, such as 80-85%). On the textured <111> surface 12 a first intrinsic layer 13 is provided, typically a Si layer, by providing a hydrogen comprising Siprecursor and hydrogen (H2) . It has been found that as such the intrinsic layer is only provided on the <111> surface and not on the <100> surface. On the first intrinsic layer 13 a first doped layer 14 is provided, which is either p- or ndoped. Dopants can be provided during e.g. deposition of the doped layer. Growth on the flat <100> substrate is found to be virtually absent (zero growth), contrary to regular growth on textured <111> surfaces (see fig. lc for schematics). Thereafter a second doped amorphous silicon layer 16 is provided, on both the textured <111> surface (now covered with the first intrinsic and first doped layer respectively), and the <100> surface. A deposition rate for the above layers is typically around 1 nm/min. The second doped layer is p-doped if the first doped layer is n-doped, and vice versa. Therewith a p-n junction is formed, suitable for e.g. PV-applications.
The present method allows for an extremely easy fabrication of a next generation of solar cells with reduction of one mask-step in the method compared to prior art.
In addition the textured surface is found to increase surface recombination. It has been found that a high aspect ratio improves energy conversion.
In an example the present method provides for a solar cell or light detector with a good efficiency (e.g. > 21%), a good series resistance (e.g. < 1 Ohm*cm), a good shunt resistance (e.g. > 1000 Ohm*cm), a good fill factor (e.g. of > 75%), and a good leakage current (e.g. < 1000 f A/cm ) . It preferably has a front side aspect ratio of >50 .
In an example the present device has a different FSF and BSF.
The present invention provides a solution to one or more of the above mentioned problems and overcomes drawbacks of the prior art.
Advantages of the present description are detailed throughout the description.
DETAILED DESCRIPTION OF THE INVENTION
In an exemplary embodiment the present method further comprises providing a second intrinsic layer 15 between the first doped layer 14 and second doped layer 16. Therewith an improved n-p junction is obtained.
In an exemplary embodiment of the present method the texturing is performed using anisotropic etching, such as wet etching, such as KOH, or Tetra-methyl ammonium hydroxide (TMAH), such as 0.1-0.5 M KOH or 0.1-0.5 Μ TMAH, during 5-30 min at a temperature between 20 and 80°C.
In an exemplary embodiment of the present method wherein the textured surface is cleaned, such as with HF. Thereby impurities and/or oxide (S1O2) is removed. Typically HF may be provided during 1-10 min at room temperature.
In an exemplary embodiment of the present method the amorphous p-layer is doped with B and the amorphous n-doped layer is doped with P.
In an exemplary embodiment of the present method the hydrogen comprising Si precursor is SiH4.
In an exemplary embodiment of the present method both the front and back side of the substrate are textured.
In an exemplary embodiment of the present method the doped amorphous layer 14,16 is provided by one or more of LPCVD, PECVD, CVD, ALD, and low pressure deposition.
In an exemplary embodiment of the present method the doped amorphous layer 14,16 is provided at a temperature of 100-300°C, during a time of 15 sec-2 hours, at a process chamber pressure of 10-1000 Pa (0.1-10 mBar).
In an exemplary embodiment of the present method the <111> textured surfaces have a width of 20-1000 pm, such as 50-500 pm, and/or wherein the textured surface has an aspect ratio (height: width of a textured structure) of 0.5-10, preferably 5-8. By anisotropic etching locally small <111> surfaces are formed, having relatively small dimension. Many adjacent surfaces having one of the <111> orientations are formed, in cross-sectional view forming zig-zag like patterns.
In an exemplary embodiment the present method further comprises passivating 17 a front side of the substrate, transparent conductive oxide (TCO) deposition 17 on the n-doped layer, patterning the TCO layer, and depositing a metal 18 on the TCO layer. The metal is typically one of Ag, Cu, Al, or W. The TCO may be an indium titanium oxide (ITO), or a doped ITO, such as hydrogen doped ITO. A passivation layer may be a silicon comprising layer, such as SiC, SiN, SiO, or a TCO.
In an exemplary embodiment of the present method one or more of the p-doped layer has a thickness of 5-50 nm, such as 10-30 nm, the first intrinsic layer has a thickness of 0.510 nm, such as 1-5 nm, the n-doped layer has a thickness of 550 nm, such as 10-30 nm, the second intrinsic layer has a thickness of 0.5-10 nm, such as 1-5 nm, the p-dopant is selected from B, the n-dopant is selected from P, and wherein dopant concentrations are in the order of 1*10 '/cm -l*10J/cm', such as 2* 101 '/cnf-5* 10ls/cm3 .
In an exemplary embodiment the present method further comprises annealing of at least one of a p-doped layer, an ndoped layer, and an intrinsic layer.
In an exemplary embodiment the present method is for producing an interdigitated back-contacted (IBC) solar cell, such as a low-cost silicon hetero-junction interdigitated back-contact solar cell, a crystalline silicon based solar cell with both n-type and p-type c-Si bulk, optionally in combination with one of a front surface field (FSF), a front floating emitter (FFE), and a passivation layer.
In a second aspect the present invention relates to a PC-cell according to claim 15.
The invention will hereafter be further elucidated through the following examples which are exemplary and explanatory of nature and are not intended to be considered limiting of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be con ceivable falling within the scope of protection, defined by the present claims.
SUMMARY OF THE FIGURES
Figures la-e show process steps of an exemplary embodiment of the present method.
DETAILED DESCRIPTION OF FIGURES
In the figures:
<100> substrate textured <111> layer intrinsic layer p-doped layer intrinsic layer n-doped layer
TCO layer metal layer
Fig. la shows a substrate with two (top and bottom, inevitably) <100> surfaces.
Figure lb shows a selective pre-texturing of a <100> surface into a <111> surface. Note that a part of the <100> surface, at a bottom right, is not textured. In this step also alignment markers may be provided.
Figure lc shows provision of an intrinsic layer and subsequent p-doped layer. In an example H2 diluted i-layer and p-a-Si:H layer deposition is provided. Only deposition occurs on textured surface, and no deposition on <100> flat surface.
Figure Id shows typical i-layer and n-layer deposition. Both occur on textured and on flat <100> surface.
Figure le shows transparent conductive oxide (TCO) deposition and patterning, as well as metallization. It is noted that
Front passivation layers deposition can be done after the texturing step.
EXPERIMENT
In an experiment various silicon layers where depositing is by using a flow rate ratio of [H2] / [SiHd >50 (>65) , as doping gas either [PH3] or [B2H6] , a pressure of > 200 Pa (2 mbar) and a power density of around or above 20 mW/cm2.
For the sake of searching the following section is added which represents a translation into English of the subsequent section .
1. Method of mask-less patterning of an amorphous silicon layer, comprising providing a Si <100> substrate (11), texturing at least one side (12), preferably a back side, of the substrate partly, thereby forming <111> surfaces, providing a first intrinsic layer (13) on the partly textured substrate only, by providing a hydrogen comprising Si-precursor and hydrogen (¾) , providing a first n- or p-doped amorphous silicon layer (14) on the intrinsic layer, by providing a hydrogen comprising Si-precursor and hydrogen (¾) , and providing a second doped amorphous silicon layer (16), wherein the second doped layer is p-doped if the first doped layer is n-doped, and vice versa.
2. Method according to embodiment 1, further comprising providing a second intrinsic layer (15) between the first doped layer (14) and second doped layer (16).
3. Method according to any of the preceding embodiments, wherein the texturing is performed using anisotropic etching, such as wet etching, such as KOH or Tetramethylammonium hydroxide (TMAH).
4. Method according to any of the preceding embodiments, wherein the textured surface is cleaned, such as with HF.
5. Method according to any of the preceding embodiments, wherein the amorphous p-doped layer is doped with B and the amorphous n-doped layer is doped with P.
6. Method according to any of the preceding embodiments wherein the hydrogen comprising Si precursor is S1H4.
7. Method according to any of the preceding embodiments wherein both the front and back side of the substrate are textured.
8. Method according to any of the preceding embodiments wherein the doped amorphous layer (14,16) is provided by one or more of LPCVD, PECVD, CVD, ALD, and low pressure deposition.
9. Method according to any of the preceding embodiments wherein the doped amorphous layer (14,16) is provided at a temperature of 100-300°C, during a time of 15 sec-2 hours, at a process chamber pressure of 10-1000 Pa (0.1-10 mBar).
10. Method according to any of the preceding embodiments, wherein the <111> textured surfaces have a width of 201000 pm, and/or wherein the textured surface has an aspect ratio (height: width of a textured structure) of 0.5-10, preferably 5-8.
11. Method according to any of the preceding embodiments, further comprising passivating (17) a front side of the substrate, transparent conductive oxide (TCO) deposition (17) on the n-doped layer, patterning the TCO layer, and depositing a metal (18) on the TCO layer.
12. Method according to any of the preceding embodiments, wherein one or more of the p-doped layer has a thickness of 5-50 nm, the first intrinsic layer has a thickness of 0.5-10 nm, the n-doped layer has a thickness of 5-50 nm, the second intrinsic layer has a thickness of 0.5-10 nm, the p-dopant is selected from B, the n-dopant is selected from P, and wherein dopant concentrations are in the order of 1 * 1017/cmö-1 * 1 0°/cm3, such as 2* 1 01'/cm3-5* 1018/cm3 .
13. Method according to any of the preceding embodiments, further comprising annealing of at least one of a p-doped layer, an n-doped layer, and an intrinsic layer.
14. Method according to any of the preceding embodiments for producing an interdigitated back-contacted (IBC) solar cell, such as a low-cost silicon hetero-junction interdigitated back-contact solar cell, a crystalline silicon based solar cell with both n-type and p-type c-Si bulk, optionally in combination with one of a front surface field (FSF), a front floating emitter (FFE), and a passivation layer.
15. PV-cell obtained by a method according to any of embodiments 1-14 .
Claims (15)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL2018491A NL2018491B1 (en) | 2017-03-09 | 2017-03-09 | Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells |
| PCT/NL2018/050140 WO2018164576A1 (en) | 2017-03-09 | 2018-03-08 | Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells |
| EP18710933.5A EP3593389A1 (en) | 2017-03-09 | 2018-03-08 | Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL2018491A NL2018491B1 (en) | 2017-03-09 | 2017-03-09 | Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells |
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| NL2018491B1 true NL2018491B1 (en) | 2018-09-21 |
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| Country | Link |
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| EP (1) | EP3593389A1 (en) |
| NL (1) | NL2018491B1 (en) |
| WO (1) | WO2018164576A1 (en) |
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| CN111354840B (en) * | 2020-04-22 | 2020-11-03 | 一道新能源科技(衢州)有限公司 | Preparation method of selective emitter double-sided PERC solar cell |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110259408A1 (en) * | 2010-04-22 | 2011-10-27 | Varian Semiconductor Equipment Associates, Inc. | Method for patterning a substrate using ion assisted selective deposition |
| EP2782144A1 (en) * | 2013-03-19 | 2014-09-24 | Imec | Method for fabricating heterojunction interdigitated back contact photovoltaic cells |
| WO2016072415A1 (en) * | 2014-11-07 | 2016-05-12 | シャープ株式会社 | Photoelectric conversion element |
| EP3021366A1 (en) * | 2014-11-17 | 2016-05-18 | Total Marketing Services | Solar cell and method of manufacturing thereof |
-
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- 2017-03-09 NL NL2018491A patent/NL2018491B1/en active
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2018
- 2018-03-08 EP EP18710933.5A patent/EP3593389A1/en active Pending
- 2018-03-08 WO PCT/NL2018/050140 patent/WO2018164576A1/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110259408A1 (en) * | 2010-04-22 | 2011-10-27 | Varian Semiconductor Equipment Associates, Inc. | Method for patterning a substrate using ion assisted selective deposition |
| EP2782144A1 (en) * | 2013-03-19 | 2014-09-24 | Imec | Method for fabricating heterojunction interdigitated back contact photovoltaic cells |
| WO2016072415A1 (en) * | 2014-11-07 | 2016-05-12 | シャープ株式会社 | Photoelectric conversion element |
| EP3021366A1 (en) * | 2014-11-17 | 2016-05-18 | Total Marketing Services | Solar cell and method of manufacturing thereof |
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| EP3593389A1 (en) | 2020-01-15 |
| WO2018164576A1 (en) | 2018-09-13 |
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