WO2018164576A1 - Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells - Google Patents

Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells Download PDF

Info

Publication number
WO2018164576A1
WO2018164576A1 PCT/NL2018/050140 NL2018050140W WO2018164576A1 WO 2018164576 A1 WO2018164576 A1 WO 2018164576A1 NL 2018050140 W NL2018050140 W NL 2018050140W WO 2018164576 A1 WO2018164576 A1 WO 2018164576A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
doped
solar cells
providing
substrate
Prior art date
Application number
PCT/NL2018/050140
Other languages
French (fr)
Inventor
Guangtao YANG
Jia Li ZHOU
Olindo ISABELLA
Miroslav Zeman
Original Assignee
Technische Universiteit Delft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technische Universiteit Delft filed Critical Technische Universiteit Delft
Priority to EP18710933.5A priority Critical patent/EP3593389A1/en
Publication of WO2018164576A1 publication Critical patent/WO2018164576A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention is in the field of a method for mask- less patterning of amorphous silicon layers, such as for low- cost silicon hetero-junction interdigitated back-contact solar cells, solar-cells and PV-panels obtainable by said method, in particular Silicon-Heteroj unction (SHJ) interdigitated back- contacted (IBC) solar cells.
  • amorphous silicon layers such as for low- cost silicon hetero-junction interdigitated back-contact solar cells, solar-cells and PV-panels obtainable by said method, in particular Silicon-Heteroj unction (SHJ) interdigitated back- contacted (IBC) solar cells.
  • SHJ Silicon-Heteroj unction
  • a solar cell, or photovoltaic (PV) cell is an electrical device that converts energy of light, typically sun light (hence "solar") , directly into electricity by the so-called photovoltaic effect.
  • the solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.
  • electrical current charge carriers of opposite types are separated.
  • the separated charge carriers are "extracted" to an external circuit, typically providing a DC-current.
  • a DC-current may be transformed into an AC- current, e.g. by using a transformer.
  • solar cells are grouped into an array of
  • Various elements may form a panel, and various panels may form a system.
  • a disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of 33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts were moved to a rear or back side, eliminating shaded areas. In addition thin silicon films were applied to the wafer. Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc. A
  • the fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is considered to be a key parameter in evaluating performance.
  • a typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt resistance; in other words less internal losses occur.
  • a disadvantage with various prior art processes for manufacturing solar cells is that a relatively high number of mask-steps is required for manufacturing, which is not cost effective .
  • silicon solar cells relate to various forms of silicon substrate, such as crystalline, amorphous and polycrystalline, which have compared to one and another different chemical and physical properties.
  • Crystalline and to some extend polycrystalline silicon may come in various crystallographic forms, such as ⁇ 100>, ⁇ 110> and ⁇ 111>, which again have compared to one and another different chemical and physical properties.
  • Teachings of different silicon substrates are therefore generally not well combined.
  • US2011/259408 Al recites a method of providing an a-Si/c-Si heteroj unction by patterning a crystalline substrate by providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate.
  • the method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate.
  • lithographic patterning is used (see [0019] ) .
  • the document is silent on the type of c-Si, on type of etching, and hence on etch-effects thereof.
  • a-Si is deposited using mixtures of silane, disilane, and/or inert gas materials, such as He, Ar, Xe and Ne.
  • EP 2 782 144 Al recites a method for forming on an
  • amorphous substrate a patterned n + a-Si:H layer and a patterned p + a-Si:H layer, the patterned n + a-Si:H layer and the
  • patterned p + a-Si:H layer being interdigitated and electrically isolated from each other, the method comprising: forming a patterned p + a-Si:H layer on the substrate, the patterned p + a- Si:H layer covering first regions of the substrate surface and leaving second regions of the substrate surface exposed;
  • a first intrinsic a-Si:H layer on the substrate; depositing an n + a-Si:H layer on the first intrinsic a-Si:H layer; providing a patterned masking layer covering the n+ a- Si:H layer at least in the second regions; and selectively removing the n + a-Si:H layer and the first intrinsic a-Si:H layer in regions not covered by the masking layer, thereby leaving the underlying p + a-Si:H layer substantially
  • selectively removing the n + a-Si:H layer and the first intrinsic a-Si:H layer comprises performing an etching step in a diluted TMAH solution.
  • WO2016/072415 Al recites a photoelectric conversion element with which it is possible to reduce the number of series resistance components and improve photoelectric conversion efficiency.
  • the photoelectric conversion element is provided with a semiconductor substrate, a first amorphous
  • semiconductor layer having a first conductor type formed on one surface of the semiconductor substrate, a second amorphous semiconductor layer having a second conductor type and formed adjacent to the first amorphous semiconductor layer in the in- plane direction of the semiconductor substrate, a first electrode formed on the first amorphous semiconductor layer, and a second electrode formed on the second amorphous
  • the film thickness reduction region extends from a first point to a second point in the in-plane direction of the semiconductor layer, where the first point is the point of the maximum film thickness, and the second point is either the point where the reduction rate of the film thickness in the in-plane direction of the semiconductor layer changes from a first reduction rate to a second reduction rate greater than the first reduction rate, or the point where the rate of change of the film thickness of the semiconductor layer in the in-plane direction of the semiconductor layer changes from negative to positive.
  • the present invention therefore relates to an improved method for mask-less patterning of amorphous silicon layers, which solve one or more of the above problems and drawbacks of the prior art, providing reliable results, without
  • the invention relates to a method of mask-less patterning of an amorphous silicon layer according to claim 1, such as in a silicon hetero-j unction
  • interdigitated back-contact solar cell In principle the method may be used in solar cells in general, such as selected from conventional homo-j unction and hetero unction solar cells, mono-facial and bi-facial solar cells, n-type and p- type mono-crystalline Si, micro-crystalline Si bulk, front contacted solar cells, back contacted solar cells, front and rear junction solar cells, and interdigitated back contacted solar cells, and combinations thereof. Contrary to prior art methods no focus plate or the like is required.
  • a Si ⁇ 100> oriented substrate 11 is provided.
  • the substrate thickness is typically in a range of 100 ⁇ -20 mm, such as 150 ⁇ -l mm.
  • For solar cells typically Si-wafers may be used, having a thickness of 150 ⁇ -300 ⁇ .
  • the substrate is textured on at least one side thereof, preferably on a back side, such as by anisotropic etching.
  • ⁇ 111> surfaces are formed, typically in a zig-zag like pattern (in cross-sectional view) .
  • a part of the surface is not textured, typically an edge-part thereof, preferably 0.2-10%, such as 1-5%, e.g. 2- 3%.
  • the non-textured surface remains a ⁇ 100> surface.
  • ⁇ 100> surface area is typically about 2-50% of the full surface area, such as 15-20% (hence 50-98% ⁇ 111> surface, such as 80-85%) .
  • a first intrinsic layer 13 is provided, typically a Si layer, by providing a hydrogen comprising Si-precursor and hydrogen (H 2 ) , such as by using a flow rate ratio of [3 ⁇ 4] / [SiH 4 ] >50 , such as >65. It has been found that as such the intrinsic layer is only provided on the ⁇ 111> surface and not on the ⁇ 100> surface, which is unexpected.
  • a first doped layer 14 is provided, which is either p- or n-doped, by providing a hydrogen comprising Si-precursor and hydrogen (H 2 ) , such as by using a flow rate ratio of [3 ⁇ 4] / [SiH 4 ] >50, such as >65.
  • Dopants can be provided during e.g. deposition of the doped layer. Growth on the flat ⁇ 100> substrate is found to be virtually absent (zero growth) , contrary to " "regular" growth on textured ⁇ 111> surfaces (see fig. lc for schematics) , which again is rather unexpected.
  • amorphous silicon layer 16 is provided, on both the textured ⁇ 111> surface (now covered with the first intrinsic and first doped layer respectively) , and the ⁇ 100> surface.
  • a deposition rate for the above layers is typically around 1 nm/min.
  • the second doped layer is p-doped if the first doped layer is n- doped, and vice versa. Therewith a p-n junction is formed, suitable for e.g. PV-applications .
  • the present method may be regarded as a self-selective deposition wherein only plasma conditions may need to be adjusted.
  • the present method allows for an extremely easy fabrication of a next generation of solar cells with reduction of one mask-step in the method compared to prior art.
  • the textured surface is found to increase surface recombination. It has been found that a high aspect ratio improves energy conversion.
  • the present method provides for a solar cell or light detector with a good efficiency (e.g. > 21%), a good series resistance (e.g. ⁇ 1 Ohm*cm) , a good shunt resistance (e.g. > 1000 Ohm*cm) , a good fill factor (e.g. of > 75%), and a good leakage current (e.g. ⁇ 1000 fA/cm 2 ) . It preferably has a front side aspect ratio of >50.
  • the present device has a different FSF and
  • the present invention provides a solution to one or more of the above mentioned problems and overcomes drawbacks of the prior art.
  • the present method may further comprise providing a second intrinsic layer 15 between the first doped layer 14 and second doped layer 16. Therewith an improved n-p junction is obtained.
  • the texturing may be performed using anisotropic etching, such as wet etching, such as KOH, or Tetra-methyl ammonium hydroxide (TMAH) , such as 0.1-0.5 KOH or 0.1-0.5 M TMAH, during 5-30 min at a temperature between 20 and 80°C.
  • anisotropic etching such as wet etching, such as KOH, or Tetra-methyl ammonium hydroxide (TMAH) , such as 0.1-0.5 KOH or 0.1-0.5 M TMAH, during 5-30 min at a temperature between 20 and 80°C.
  • the textured surface may be cleaned, such as with HF. Thereby impurities and/or oxide (S1O2) are/is removed.
  • HF may be provided during 1-10 min at room temperature.
  • the amorphous p-layer may be doped with B and the amorphous n- doped layer is doped with P.
  • the hydrogen comprising Si precursor may be SiH4.
  • both the front and back side of the substrate may be textured.
  • the doped amorphous layer 14,16 may be provided by one or more of LPCVD, PECVD, CVD, ALD, and low pressure deposition.
  • the doped amorphous layer 14,16 may be provided at a temperature of 100- 300 °C, during a time of 15 sec-2 hours, at a process chamber pressure of 10-1000 Pa (0.1-10 mBar) .
  • the ⁇ 111> textured surfaces may have a width of 20-1000 um, such as 50- 500 um, and/or wherein the textured surface may have an aspect ratio (height : width of a textured structure) of 0.5-10, preferably 5-8.
  • anisotropic etching locally small ⁇ 111> surfaces are formed, having relatively small dimension. Many adjacent surfaces having one of the ⁇ 111> orientations may be formed, in cross-sectional view forming zig-zag like patterns.
  • the present method may further comprise passivating 19 a front side of the substrate,
  • TCO transparent conductive oxide
  • the metal is typically one of Ag, Cu, Al, or W.
  • the TCO may be an indium titanium oxide (ITO) , or a doped ITO, such as hydrogen doped ITO.
  • a passivation layer may be a silicon comprising layer, such as SiC, SiN, SiO, or a CO.
  • one or more of the p-doped layer may have a thickness of 5-50 nm, such as 10-30 nm, the first intrinsic layer may have a
  • the n-doped layer may have a thickness of 5-50 nm, such as 10-30 nm
  • the second intrinsic layer may have a thickness of 0.5-10 nm, such as 1-5 nm
  • the p-dopant is selected from B
  • the n-dopant is selected from P
  • dopant concentrations may be in the order of l ⁇ 10 17 /cm 3 -l*10 20 /cm 3 , such as 2*10 17 /cm 3 -5*10 18 /cm 3 .
  • the present method may further comprise annealing of at least one of a p-doped layer, an n- doped layer, and an intrinsic layer.
  • the present method may be for producing an interdigitated back-contacted (IBC) solar cell, such as a low-cost silicon hetero-junction interdigitated back-contact solar cell, a crystalline silicon based solar cell with both n-type and p-type c-Si bulk, optionally in combination with one of a front surface field (FSF) , a front floating emitter (FFE) , and a passivation layer.
  • IBC interdigitated back-contacted
  • FSF front surface field
  • FFE front floating emitter
  • the present invention relates to a PV- cell according to claim 15.
  • This PV-cell distinguishes over the prior art in various structural aspects, such as a Si ⁇ 100> substrate, a partly structured substrate, ⁇ 111> textured surfaces, a first intrinsic layer 13 on the partly textured substrate only, and a first n- or p-doped amorphous silicon layer 14 on the intrinsic layer (which is selectively
  • Figures la-e show process steps of an exemplary embodiment of the present method.
  • Fig. la shows a substrate 11 with two (top and bottom, inevitably) ⁇ 100> surfaces.
  • Figure lb shows a selective pre-texturing of a ⁇ 100> surface into a ⁇ 111> surface 12. Note that a part of the ⁇ 100> surface, at a bottom right, may not be textured. In this step also alignment markers may be provided.
  • Figure lc shows provision of an intrinsic layer 13 and subsequent p-doped layer 14.
  • 3 ⁇ 4 diluted i-layer and p-a-Si:H layer deposition is provided. Only deposition occurs on textured surface, and no deposition on ⁇ 100> flat surface .
  • Figure Id shows typical i-layer 15 and n-layer 16
  • Figure le shows transparent conductive oxide (TCO) 17 deposition and patterning, as well as metallization 18. It is noted that Front passivation layers 19 deposition can be done after the texturing step.
  • TCO transparent conductive oxide

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The present invention is in the field of a method for mask-less patterning of amorphous silicon layers, such as for low-cost silicon hetero-junction interdigitated back-contact solar cells, solar-cells and PV-panels obtainable by said method, in particular Silicon-Heterojunction (SHJ) interdigitated back-contacted (IBC) solar cells.

Description

Title: Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells FIELD OF THE INVENTION
The present invention is in the field of a method for mask- less patterning of amorphous silicon layers, such as for low- cost silicon hetero-junction interdigitated back-contact solar cells, solar-cells and PV-panels obtainable by said method, in particular Silicon-Heteroj unction (SHJ) interdigitated back- contacted (IBC) solar cells.
BACKGROUND OF THE INVENTION
A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence "solar") , directly into electricity by the so-called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.
Solar cells are described as being photovoltaic
irrespective of whether the source is sunlight or an
artificial light. They may also be used as photo detector.
When a solar cell absorbs light it may generate either electron-hole pairs or excitons. In order to obtain an
electrical current charge carriers of opposite types are separated. The separated charge carriers are "extracted" to an external circuit, typically providing a DC-current. For practical use a DC-current may be transformed into an AC- current, e.g. by using a transformer.
Typically solar cells are grouped into an array of
elements. Various elements may form a panel, and various panels may form a system.
A disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of 33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts were moved to a rear or back side, eliminating shaded areas. In addition thin silicon films were applied to the wafer. Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc. A
qualification of performance of a solar cell is the fill factor (FF) . The fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is considered to be a key parameter in evaluating performance. A typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt resistance; in other words less internal losses occur.
Efficiency is nevertheless improving gradually, so every relatively small improvement is welcomed and of significant importance .
A disadvantage with various prior art processes for manufacturing solar cells is that a relatively high number of mask-steps is required for manufacturing, which is not cost effective .
Many of the prior art silicon solar cells relate to various forms of silicon substrate, such as crystalline, amorphous and polycrystalline, which have compared to one and another different chemical and physical properties. Crystalline and to some extend polycrystalline silicon may come in various crystallographic forms, such as <100>, <110> and <111>, which again have compared to one and another different chemical and physical properties. Teachings of different silicon substrates are therefore generally not well combined.
The below prior art documents recite solar cells with amorphous layers. However these suffer from various
disadvantages. Amongst others complex fabrication, many mask- steps, limited surface recombination, a limited energy
conversion, a relatively poor shunt resistance and series resistance, a limited fill factor, and a poor leakage current .
US2011/259408 Al recites a method of providing an a-Si/c-Si heteroj unction by patterning a crystalline substrate by providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate. Thereto lithographic patterning is used (see [0019] ) . The document is silent on the type of c-Si, on type of etching, and hence on etch-effects thereof. In an example a-Si is deposited using mixtures of silane, disilane, and/or inert gas materials, such as He, Ar, Xe and Ne.
EP 2 782 144 Al recites a method for forming on an
amorphous substrate a patterned n+ a-Si:H layer and a patterned p+ a-Si:H layer, the patterned n+ a-Si:H layer and the
patterned p+ a-Si:H layer being interdigitated and electrically isolated from each other, the method comprising: forming a patterned p+ a-Si:H layer on the substrate, the patterned p+ a- Si:H layer covering first regions of the substrate surface and leaving second regions of the substrate surface exposed;
depositing a first intrinsic a-Si:H layer on the substrate; depositing an n+ a-Si:H layer on the first intrinsic a-Si:H layer; providing a patterned masking layer covering the n+ a- Si:H layer at least in the second regions; and selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer in regions not covered by the masking layer, thereby leaving the underlying p+ a-Si:H layer substantially
unaffected, wherein selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer comprises performing an etching step in a diluted TMAH solution.
WO2016/072415 Al recites a photoelectric conversion element with which it is possible to reduce the number of series resistance components and improve photoelectric conversion efficiency. The photoelectric conversion element is provided with a semiconductor substrate, a first amorphous
semiconductor layer having a first conductor type formed on one surface of the semiconductor substrate, a second amorphous semiconductor layer having a second conductor type and formed adjacent to the first amorphous semiconductor layer in the in- plane direction of the semiconductor substrate, a first electrode formed on the first amorphous semiconductor layer, and a second electrode formed on the second amorphous
semiconductor layer. The film thickness reduction region extends from a first point to a second point in the in-plane direction of the semiconductor layer, where the first point is the point of the maximum film thickness, and the second point is either the point where the reduction rate of the film thickness in the in-plane direction of the semiconductor layer changes from a first reduction rate to a second reduction rate greater than the first reduction rate, or the point where the rate of change of the film thickness of the semiconductor layer in the in-plane direction of the semiconductor layer changes from negative to positive.
The present invention therefore relates to an improved method for mask-less patterning of amorphous silicon layers, which solve one or more of the above problems and drawbacks of the prior art, providing reliable results, without
jeopardizing functionality and advantages.
SUMMARY OF THE INVENTION
It is an object of the invention to overcome one or more limitations of the methods and devices of the prior art and at the very least to provide an alternative thereto.
In a first aspect, the invention relates to a method of mask-less patterning of an amorphous silicon layer according to claim 1, such as in a silicon hetero-j unction
interdigitated back-contact solar cell. In principle the method may be used in solar cells in general, such as selected from conventional homo-j unction and hetero unction solar cells, mono-facial and bi-facial solar cells, n-type and p- type mono-crystalline Si, micro-crystalline Si bulk, front contacted solar cells, back contacted solar cells, front and rear junction solar cells, and interdigitated back contacted solar cells, and combinations thereof. Contrary to prior art methods no focus plate or the like is required. Therein a Si<100> oriented substrate 11 is provided. The substrate thickness is typically in a range of 100 μπι-20 mm, such as 150 μιιι-l mm. For solar cells typically Si-wafers may be used, having a thickness of 150 μπι-300 μηα. The substrate is textured on at least one side thereof, preferably on a back side, such as by anisotropic etching. Thereby <111> surfaces are formed, typically in a zig-zag like pattern (in cross-sectional view) . Contrary to typical prior art, such as recited in the above documents, a part of the surface is not textured, typically an edge-part thereof, preferably 0.2-10%, such as 1-5%, e.g. 2- 3%. The non-textured surface remains a <100> surface. The
<100> surface area is typically about 2-50% of the full surface area, such as 15-20% (hence 50-98% <111> surface, such as 80-85%) . On the textured <111> surface 12 a first intrinsic layer 13 is provided, typically a Si layer, by providing a hydrogen comprising Si-precursor and hydrogen (H2) , such as by using a flow rate ratio of [¾] / [SiH4] >50 , such as >65. It has been found that as such the intrinsic layer is only provided on the <111> surface and not on the <100> surface, which is unexpected. On the first intrinsic layer 13 a first doped layer 14 is provided, which is either p- or n-doped, by providing a hydrogen comprising Si-precursor and hydrogen (H2) , such as by using a flow rate ratio of [¾] / [SiH4] >50, such as >65. Dopants can be provided during e.g. deposition of the doped layer. Growth on the flat <100> substrate is found to be virtually absent (zero growth) , contrary to ""regular" growth on textured <111> surfaces (see fig. lc for schematics) , which again is rather unexpected. Thereafter a second doped
amorphous silicon layer 16 is provided, on both the textured <111> surface (now covered with the first intrinsic and first doped layer respectively) , and the <100> surface. A deposition rate for the above layers is typically around 1 nm/min. The second doped layer is p-doped if the first doped layer is n- doped, and vice versa. Therewith a p-n junction is formed, suitable for e.g. PV-applications . The present method may be regarded as a self-selective deposition wherein only plasma conditions may need to be adjusted.
The present method allows for an extremely easy fabrication of a next generation of solar cells with reduction of one mask-step in the method compared to prior art.
In addition the textured surface is found to increase surface recombination. It has been found that a high aspect ratio improves energy conversion.
In an example the present method provides for a solar cell or light detector with a good efficiency (e.g. > 21%), a good series resistance (e.g. < 1 Ohm*cm) , a good shunt resistance (e.g. > 1000 Ohm*cm) , a good fill factor (e.g. of > 75%), and a good leakage current (e.g. < 1000 fA/cm2) . It preferably has a front side aspect ratio of >50.
In an example the present device has a different FSF and
BSF.
The present invention provides a solution to one or more of the above mentioned problems and overcomes drawbacks of the prior art.
Advantages of the present description are detailed
throughout the description.
DETAILED DESCRIPTION OF THE INVENTION
In an exemplary embodiment the present method may further comprise providing a second intrinsic layer 15 between the first doped layer 14 and second doped layer 16. Therewith an improved n-p junction is obtained.
In an exemplary embodiment of the present method the texturing may be performed using anisotropic etching, such as wet etching, such as KOH, or Tetra-methyl ammonium hydroxide (TMAH) , such as 0.1-0.5 KOH or 0.1-0.5 M TMAH, during 5-30 min at a temperature between 20 and 80°C.
In an exemplary embodiment of the present method the textured surface may be cleaned, such as with HF. Thereby impurities and/or oxide (S1O2) are/is removed. Typically HF may be provided during 1-10 min at room temperature.
In an exemplary embodiment of the present method the amorphous p-layer may be doped with B and the amorphous n- doped layer is doped with P.
In an exemplary embodiment of the present method the hydrogen comprising Si precursor may be SiH4.
In an exemplary embodiment of the present method both the front and back side of the substrate may be textured.
In an exemplary embodiment of the present method the doped amorphous layer 14,16 may be provided by one or more of LPCVD, PECVD, CVD, ALD, and low pressure deposition.
In an exemplary embodiment of the present method the doped amorphous layer 14,16 may be provided at a temperature of 100- 300 °C, during a time of 15 sec-2 hours, at a process chamber pressure of 10-1000 Pa (0.1-10 mBar) . In an exemplary embodiment of the present method the <111> textured surfaces may have a width of 20-1000 um, such as 50- 500 um, and/or wherein the textured surface may have an aspect ratio (height : width of a textured structure) of 0.5-10, preferably 5-8. By anisotropic etching locally small <111> surfaces are formed, having relatively small dimension. Many adjacent surfaces having one of the <111> orientations may be formed, in cross-sectional view forming zig-zag like patterns.
In an exemplary embodiment the present method may further comprise passivating 19 a front side of the substrate,
transparent conductive oxide (TCO) deposition 17 on the n- doped layer, patterning the TCO layer, and depositing a metal 18 on the TCO layer. The metal is typically one of Ag, Cu, Al, or W. The TCO may be an indium titanium oxide (ITO) , or a doped ITO, such as hydrogen doped ITO. A passivation layer may be a silicon comprising layer, such as SiC, SiN, SiO, or a CO.
In an exemplary embodiment of the present method one or more of the p-doped layer may have a thickness of 5-50 nm, such as 10-30 nm, the first intrinsic layer may have a
thickness of 0.5-10 nm, such as 1-5 nm, the n-doped layer may have a thickness of 5-50 nm, such as 10-30 nm, the second intrinsic layer may have a thickness of 0.5-10 nm, such as 1-5 nm, the p-dopant is selected from B, the n-dopant is selected from P, and wherein dopant concentrations may be in the order of l÷1017/cm3-l*1020/cm3, such as 2*1017/cm3-5*1018/cm3.
In an exemplary embodiment the present method may further comprise annealing of at least one of a p-doped layer, an n- doped layer, and an intrinsic layer.
In an exemplary embodiment the present method may be for producing an interdigitated back-contacted (IBC) solar cell, such as a low-cost silicon hetero-junction interdigitated back-contact solar cell, a crystalline silicon based solar cell with both n-type and p-type c-Si bulk, optionally in combination with one of a front surface field (FSF) , a front floating emitter (FFE) , and a passivation layer.
In a second aspect the present invention relates to a PV- cell according to claim 15. This PV-cell distinguishes over the prior art in various structural aspects, such as a Si <100> substrate, a partly structured substrate, <111> textured surfaces, a first intrinsic layer 13 on the partly textured substrate only, and a first n- or p-doped amorphous silicon layer 14 on the intrinsic layer (which is selectively
deposited on the textured substrate only) , and in the obtained advantages, as detailed throughout the description.
The invention will hereafter be further elucidated through the following examples which are exemplary and explanatory of nature and are not intended to be considered limiting of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims .
SUMMARY OF THE FIGURES
Figures la-e show process steps of an exemplary embodiment of the present method.
DETAILED DESCRIPTION OF FIGURES
In the figures:
11 <100> substrate
12 textured <111> layer
13 intrinsic layer
14 p-doped layer
15 intrinsic layer
16 n-doped layer
17 TCO layer
18 metal layer
19 passivation layer
Fig. la shows a substrate 11 with two (top and bottom, inevitably) <100> surfaces.
Figure lb shows a selective pre-texturing of a <100> surface into a <111> surface 12. Note that a part of the <100> surface, at a bottom right, may not be textured. In this step also alignment markers may be provided.
Figure lc shows provision of an intrinsic layer 13 and subsequent p-doped layer 14. In an example ¾ diluted i-layer and p-a-Si:H layer deposition is provided. Only deposition occurs on textured surface, and no deposition on <100> flat surface .
Figure Id shows typical i-layer 15 and n-layer 16
deposition. Both occur on textured and on flat <100> surface.
Figure le shows transparent conductive oxide (TCO) 17 deposition and patterning, as well as metallization 18. It is noted that Front passivation layers 19 deposition can be done after the texturing step.
EXPERIMENT
In an experiment various silicon layers where depositing is by using a flow rate ratio of [¾] / [SiH4] >50 (>65) , as doping gas either [PH3] or [B2H6] , a pressure of > 200 Pa {2 nibar) and a power density of around or above 20 mW/cm2.

Claims

1. Method of mask-less patterning of an amorphous silicon layer in a solar cell, comprising
providing a Si <100> substrate (11) ,
texturing at least one side (12), preferably a back side, of the substrate partly, thereby forming <111> surfaces, providing a first intrinsic layer (13) on the partly textured substrate only, by providing a hydrogen
comprising Si-precursor and hydrogen (H2) ,
providing a first n- or p-doped amorphous silicon layer (14) on the intrinsic layer, by providing a hydrogen comprising Si-precursor and hydrogen (¾) , and
providing a second doped amorphous silicon layer (16), wherein the second doped layer is p-doped if the first doped layer is n-doped, and vice versa.
2. Method according to claim 1, further comprising
providing a second intrinsic layer (15) between the first doped layer (14) and second doped layer (16) .
3. Method according to any of the preceding claims, wherein the texturing is performed using anisotropic etching.
4. Method according to claim 3, wherein anisotropic etching is selected from wet etching, KOH, and Tetramethylammonium hydroxide (TMAH) .
5. Method according to any of the preceding claims, wherein the textured surface is cleaned.
6. Method according to claim 5, wherein the textured surface is cleaned with HF.
7. Method according to any of the preceding claims, wherein the amorphous p-doped layer is doped with B and the amorphous n-doped layer is doped with P.
8. Method according to any of the preceding claims, wherein the hydrogen comprising Si precursor is SiH .
9. Method according to any of the preceding claims wherein both the front and back side of the substrate are textured.
10. Method according to any of the preceding claims wherein the doped amorphous layer (14,16) is provided by one or more of LPCVD, PECVD, CVD, ALD, and low pressure deposition.
11. Method according to any of the preceding claims wherein the doped amorphous layer (14,16) is provided at a temperature of 100-300 °C, during a time of 15 sec-2 hours, at a process chamber pressure of 10-1000 Pa (0.1-10 mBar) .
12. Method according to any of the preceding claims, wherein the <111> textured surfaces have a width of 20-1000 um, and/or
wherein the textured surface has an aspect ratio (height : width of a textured structure) of 0.5-10, preferably 5-8.
13. Method according to any of the preceding claims, further comprising
passivating (19) a front side of the substrate,
transparent conductive oxide (TCO) deposition (17} on the n-doped layer,
patterning the TCO layer, and
depositing a metal (18) on the TCO layer.
14. Method according to any of the preceding claims, wherein one or more of
the p-doped layer has a thickness of 5-50 nm,
the first intrinsic layer has a thickness of 0.5-10 nm, the n-doped layer has a thickness of 5-50 nm,
the second intrinsic layer has a thickness of 0.5-10 nm, the p-dopant is selected from B,
the n-dopant is selected from P, and
wherein dopant concentrations are in the order of l*1017/cm3- l*1020/cm3,
15. Method according to claim 5, wherein the dopant concentrations are in the order of 2*l017/cm3-5*1018/cm3.
16. Method according to any of the preceding claims, further comprising annealing of at least one of a p-doped layer, an n-doped layer, and an intrinsic layer.
17. Method according to any of the preceding claims for producing an interdigitated back-contacted (IBC) solar cell, a low-cost silicon hetero- unction interdigitated back-contact solar cell, or a crystalline silicon based solar cell with both n-type and p-type c-Si bulk.
18. Method according to claim 17, in combination with providing one of a front surface field (FSF) , a front floating emitter (FFE) , and a passivation layer (19) .
19. PV-cell obtained by a method according to any of claims 1-18.
20. PV-cell according to claim 19, wherein the PV-cell is selected from conventional homo-junction and heterojunction solar cells, mono-facial and bi-facial solar cells, n-type and p-type mono-crystalline Si, micro-crystalline Si bulk, front contacted solar cells, back contacted solar cells, front and rear junction solar cells, and interdigitated back contacted solar cells, and combinations thereof.
PCT/NL2018/050140 2017-03-09 2018-03-08 Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells WO2018164576A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP18710933.5A EP3593389A1 (en) 2017-03-09 2018-03-08 Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL2018491A NL2018491B1 (en) 2017-03-09 2017-03-09 Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells
NL2018491 2017-03-09

Publications (1)

Publication Number Publication Date
WO2018164576A1 true WO2018164576A1 (en) 2018-09-13

Family

ID=58455622

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL2018/050140 WO2018164576A1 (en) 2017-03-09 2018-03-08 Mask-less patterning of amorphous silicon layers for low-cost silicon hetero-junction interdigitated back-contact solar cells

Country Status (3)

Country Link
EP (1) EP3593389A1 (en)
NL (1) NL2018491B1 (en)
WO (1) WO2018164576A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111354840A (en) * 2020-04-22 2020-06-30 一道新能源科技(衢州)有限公司 Preparation method of selective emitter double-sided PERC solar cell
CN115050856A (en) * 2022-06-23 2022-09-13 苏州迈为科技股份有限公司 Heterojunction solar cell and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110259408A1 (en) 2010-04-22 2011-10-27 Varian Semiconductor Equipment Associates, Inc. Method for patterning a substrate using ion assisted selective deposition
EP2782144A1 (en) 2013-03-19 2014-09-24 Imec Method for fabricating heterojunction interdigitated back contact photovoltaic cells
WO2016072415A1 (en) 2014-11-07 2016-05-12 シャープ株式会社 Photoelectric conversion element
EP3021366A1 (en) * 2014-11-17 2016-05-18 Total Marketing Services Solar cell and method of manufacturing thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110259408A1 (en) 2010-04-22 2011-10-27 Varian Semiconductor Equipment Associates, Inc. Method for patterning a substrate using ion assisted selective deposition
EP2782144A1 (en) 2013-03-19 2014-09-24 Imec Method for fabricating heterojunction interdigitated back contact photovoltaic cells
WO2016072415A1 (en) 2014-11-07 2016-05-12 シャープ株式会社 Photoelectric conversion element
EP3021366A1 (en) * 2014-11-17 2016-05-18 Total Marketing Services Solar cell and method of manufacturing thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111354840A (en) * 2020-04-22 2020-06-30 一道新能源科技(衢州)有限公司 Preparation method of selective emitter double-sided PERC solar cell
CN115050856A (en) * 2022-06-23 2022-09-13 苏州迈为科技股份有限公司 Heterojunction solar cell and preparation method thereof

Also Published As

Publication number Publication date
EP3593389A1 (en) 2020-01-15
NL2018491B1 (en) 2018-09-21

Similar Documents

Publication Publication Date Title
US8872020B2 (en) Heterojunction solar cell based on epitaxial crystalline-silicon thin film on metallurgical silicon substrate design
KR101000064B1 (en) Hetero-junction silicon solar cell and fabrication method thereof
US7943416B2 (en) Local heterostructure contacts
US8288645B2 (en) Single heterojunction back contact solar cell
US10084107B2 (en) Transparent conducting oxide for photovoltaic devices
EP2016627B1 (en) Solar cell having doped semiconductor heterojunction contacts
EP2996163B1 (en) Photoelectric conversion device and manufacturing method thereof
US20140102524A1 (en) Novel electron collectors for silicon photovoltaic cells
US20100243042A1 (en) High-efficiency photovoltaic cells
US20140283902A1 (en) Back junction solar cell with tunnel oxide
US20080173347A1 (en) Method And Apparatus For A Semiconductor Structure
US20090255574A1 (en) Solar cell fabricated by silicon liquid-phase deposition
EP2385561A2 (en) Solar Cell
US9865754B2 (en) Hole collectors for silicon photovoltaic cells
JP2008021993A (en) Photovoltaic device including all-back-contact configuration, and related method
CN102064216A (en) Novel crystalline silicon solar cell and manufacturing method thereof
AU2008200051A1 (en) Method and apparatus for a semiconductor structure forming at least one via
US20130157404A1 (en) Double-sided heterojunction solar cell based on thin epitaxial silicon
WO2016068711A2 (en) Back side contacted wafer-based solar cells with in-situ doped crystallized silicon oxide regions
EP3021366A1 (en) Solar cell and method of manufacturing thereof
US11251325B2 (en) Photovoltaic device and method for manufacturing the same
KR101886818B1 (en) Method for manufacturing of heterojunction silicon solar cell
CN111952381B (en) Silicon heterojunction solar cell and preparation method thereof
CN110752274A (en) Method for manufacturing HBC battery piece and battery by using shadow mask film coating
JPS62234379A (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18710933

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018710933

Country of ref document: EP

Effective date: 20191009