CN115050856A - Heterojunction solar cell and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000004065 semiconductor Substances 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 61
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000003513 alkali Substances 0.000 claims description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 18
- 238000003486 chemical etching Methods 0.000 claims description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 3
- 239000001272 nitrous oxide Substances 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 461
- 239000010408 film Substances 0.000 description 32
- 239000000243 solution Substances 0.000 description 30
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 239000000976 ink Substances 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000012670 alkaline solution Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910014558 c-SiO Inorganic materials 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000004050 hot filament vapor deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000036632 reaction speed Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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Abstract
The application discloses a heterojunction solar cell and a preparation method thereof, and belongs to the technical field of solar cells. A method of fabricating a heterojunction solar cell, the method comprising: patterning the back of the semiconductor substrate to form a first doping area and a second doping area, wherein the first doping area is provided with a first intrinsic i layer and an n-type doping layer, and the n-type doping layer is an oxygen-doped microcrystalline silicon layer doped with VA group elements; forming a second intrinsic i layer and a p-type doped layer, wherein the p-type doped layer is an amorphous or microcrystalline silicon layer doped with IIIA group elements; and forming a patterned mask layer on the second intrinsic i layer and the p-type doped layer, exposing the second intrinsic i layer and the p-type doped layer on the first doped region, removing the exposed second intrinsic i layer and the exposed p-type doped layer, and keeping the first intrinsic i layer and the n-type doped layer. The invention can simplify the preparation process, reduce the pollution risk caused by the isolation layer entering the cavity and reduce the complicated steps of adding or removing the isolation layer.
Description
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a heterojunction solar cell and a preparation method thereof.
Background
As a new solar cell, the heterojunction solar cell has become a new hotspot in the photovoltaic field in recent years, and has many advantages of simple structure, wide raw material sources, high open-circuit voltage, high conversion efficiency, low temperature coefficient, and the like. The back contact solar cell has the advantages that the front surface of the back contact solar cell is not provided with the main grid lines, even any electrode patterns, and the positive electrode and the negative electrode are arranged on the back surface of the cell, so that the shading of the cell is reduced, the short-circuit current of the cell is effectively increased, and the energy conversion efficiency of the cell is improved. The back contact Heterojunction (HBC) cell is a crystalline silicon solar cell with relatively high photoelectric conversion efficiency at present, is a combination of a Heterojunction (HJT) technology and a back contact (IBC) technology, has many advantages of two cell structures, and as an end electrode structure of a high-efficiency single-crystal silicon cell, the back contact heterojunction cell has occupied a treasure for recording the highest conversion efficiency of the crystalline silicon cell in recent years.
The realization of the back interdigital structure of the traditional back contact heterojunction solar cell at least needs three patterning processes and multiple cleaning steps, and the multiple high-precision patterning processes and the multiple cleaning steps greatly improve the difficulty and the cost of the preparation process of the back contact heterojunction solar cell, and limit the industrial application progress of the back contact heterojunction solar cell due to the factors of complicated preparation procedures, complex manufacturing procedures and the like. Therefore, there is a need for an improved method of fabricating back contact heterojunction solar cells.
Disclosure of Invention
In view of the above-mentioned problems, the present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the invention provides the heterojunction solar cell and the preparation method thereof, which can simplify the preparation process, reduce the pollution risk caused by the fact that the isolation layer (ink or dry film) enters the cavity, reduce the complicated steps of adding or removing the isolation layer and overcome the defects in the prior art.
In order to solve the technical problem, the present application is implemented as follows:
according to one aspect of the present application, there is provided a method of fabricating a heterojunction solar cell, the method comprising:
patterning the back of the semiconductor substrate to form a first doping region and a second doping region which are arranged in a staggered mode, wherein the first doping region is provided with a first intrinsic i layer and an n-type doping layer, and the n-type doping layer is an oxygen-doped microcrystalline silicon layer doped with VA group elements;
forming a second intrinsic i layer and a p-type doped layer on the first doped region and the second doped region, wherein the p-type doped layer is an amorphous or microcrystalline silicon layer doped with a group IIIA element;
forming a patterned mask layer on the second intrinsic i layer and the p-type doped layer, wherein the patterned mask layer exposes the second intrinsic i layer and the p-type doped layer on the first doped region, and the exposed second intrinsic i layer and the exposed p-type doped layer are removed while the first intrinsic i layer and the exposed n-type doped layer are reserved;
and removing the patterned mask layer, and forming the second intrinsic i layer and the p-type doped layer in the second doped region.
In some embodiments, the patterning on the back side of the semiconductor substrate to form the first doped region and the second doped region in a staggered arrangement, the first doped region formed with the first intrinsic i layer and the n-type doped layer specifically includes:
forming the first intrinsic i layer and the n-type doped layer on the back surface of the semiconductor substrate;
preparing masks on the surfaces of the first intrinsic i layer and the n-type doped layer, and exposing and developing to form a patterned mask layer;
removing the first intrinsic i layer and the n-type doped layer which are not covered by the mask to form the second doped region;
and removing the patterned mask layer to form the first intrinsic i layer and the n-type doped layer in the first doped region.
In some embodiments, the first intrinsic i layer and/or the second intrinsic i layer has a thickness of 5nm to 20nm, and the second intrinsic i layer covers upper and side surfaces of the first intrinsic i layer and the n-type doped layer within the first doped region.
In some embodiments, the forming a patterned mask layer on the second intrinsic i-layer and the p-type doped layer, the patterned mask layer exposing the second intrinsic i-layer and the p-type doped layer on the first doped region, and the removing the exposed second intrinsic i-layer and the p-type doped layer and leaving the first intrinsic i-layer and the n-type doped layer specifically includes:
preparing masks on the surfaces of the second intrinsic i layer and the p-type doped layer, and exposing and developing to form a patterned mask layer;
the second intrinsic i layer and the p-type doped layer on the first doped region are exposed out of the patterned mask layer;
and removing the second intrinsic i layer and the p-type doped layer exposed outside by adopting a chemical etching mode, wherein the etching rate of the second intrinsic i layer and the p-type doped layer is greater than that of the n-type doped layer, so that the first intrinsic i layer and the n-type doped layer below the second intrinsic i layer and the p-type doped layer are reserved.
In some embodiments, the process conditions of the chemical etching include:
etching by using alkali liquor, wherein the mass concentration of the alkali liquor is not more than 1.5%;
the etching temperature is 18-35 ℃.
In some embodiments, the removing the patterned mask layer further includes, after the second doped region is formed with the second intrinsic i layer and the p-type doped layer:
preparing back TCO layers on the surfaces of the first intrinsic i layer, the n-type doped layer, the second intrinsic i layer and the p-type doped layer;
and preparing a metal electrode on the surface of the back TCO layer and patterning the back TCO layer and the metal electrode.
In some embodiments, the metal electrode patterning includes a first gate line electrode on a first intrinsic i layer and an n-type doped layer, and a second gate line electrode on a second intrinsic i layer and a p-type doped layer;
the width of the first grid line electrode is 50-300 mu m, the width of the second grid line electrode is 500-1200 mu m, and the distance between the first grid line electrode and the second grid line electrode is 100-500 mu m.
In some of these embodiments, the method further comprises:
forming a first intrinsic i layer and an n-type doped layer on the front surface of a semiconductor substrate;
and forming a front antireflection layer on the surfaces of the first intrinsic i layer and the n-type doped layer.
In some embodiments, the process step of forming the n-doped layer comprises: carbon dioxide and/or nitrous oxide are used as an oxygen source, and the flow ratio of the oxygen source to silane is 1: 8-2: 1.
According to another aspect of the present application, there is provided a heterojunction solar cell comprising:
a semiconductor substrate;
the back surface of the semiconductor substrate is sequentially provided with a doping layer, a back TCO layer and a metal electrode, wherein the doping layer is composed of a first doping region and a second doping region, the first doping region and the second doping region are arranged in a staggered mode in an interdigital mode, the first doping region is provided with a first intrinsic i layer and an n-type doping layer, and the second doping region is provided with a second intrinsic i layer and a p-type doping layer;
the front surface of the semiconductor substrate is sequentially provided with a first intrinsic i layer, an n-type doping layer and a front surface antireflection layer.
It should be noted that the above numerical ranges are inclusive of the endpoints.
The technical scheme of the invention at least has the following beneficial effects:
in the preparation process of the heterojunction solar cell, a first intrinsic i layer and an n-type doped layer are formed in a first doped region, wherein the n-type doped layer is an oxygen-doped microcrystalline silicon layer doped with a VA group element, so that the n-type doped layer (the oxygen-doped microcrystalline silicon layer) and an amorphous i layer (a non-oxygen-doped non-microcrystalline silicon layer) can be utilized when removing a second intrinsic i layer and a p-type doped layer on the first doped regionSilicon layer) and an etching solution, and removing the second intrinsic i layer and the p-type doped layer above the first doped region in one step in place and enabling the first intrinsic i layer and the n-type doped layer below the first doped region to be retained. Thus, the invention can use the original less controllable non-intermediate isolation layer (such as printing ink or dry film, SiO) x Or SiN x Etc.) etching the second intrinsic i layer and the p-type doped layer becomes controllable; without the need to retain an isolation layer (such as ink or dry film) into the chamber, the risk of contamination is reduced or avoided, and no additional isolation layer (such as SiO) is required x Or SiN x Etc.) and the complicated step of removing the isolating layer, simplifies the preparation process, has simple preparation flow and improves the production efficiency.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic diagram of step S110 in a method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 2 is a schematic diagram of step S120 in a method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 3 is a schematic diagram of step S130 in a method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 4 is a schematic diagram of step S140 in a method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 5 is a schematic diagram of step S200 in the method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 6 is a schematic diagram of step S300 in a method for fabricating a heterojunction solar cell according to some embodiments of the present invention;
fig. 7 is a schematic diagram of step S400 in a method for fabricating a heterojunction solar cell according to some embodiments of the present invention;
fig. 8 is a schematic diagram of step S510 in a method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 9 is a schematic diagram of step S520 in a method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 10 is a schematic diagram of step S530 in the method for manufacturing a heterojunction solar cell according to some embodiments of the present invention;
fig. 11 is a schematic diagram of step S540 of a method for fabricating a heterojunction solar cell according to some embodiments of the present invention;
figure 12 is a schematic diagram of a heterojunction solar cell provided by some embodiments of the present invention.
Description of reference numerals:
10-a semiconductor substrate;
20-a first intrinsic i layer and an n-doped layer;
31-a patterned mask layer; 32-mask (ink or dry film);
40-a second intrinsic i layer and a p-type doped layer;
51-back TCO layer; 52-front anti-reflection layer;
60-copper seed layer;
70-a metal electrode; 71-a first gate line electrode; 72-a second gate line electrode.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The endpoints of the ranges and any values disclosed herein are not limited to the precise range or value, and such ranges or values should be understood to encompass values close to those ranges or values. For numerical ranges, one or more new numerical ranges may be obtained by combining the individual values, or by combining the individual values.
In the related art, in order to solve the above problems,the back side of a back contact heterojunction (HJT-IBC, i.e., HBC) solar cell has an n-type region and a p-type region, the n-type region is formed by growing an intrinsic i layer and a phosphorus-doped n layer on the back side of a silicon substrate, and the p-type region is formed by growing an intrinsic i layer and a boron-doped p layer on the back side of the silicon substrate, which requires complicated mask preparation and removal steps for n-region selectivity and p-region selectivity. Usually, dry films or inks or inorganic SiO are used in the preparation process x 、SiN x And the like are used as an intermediate isolation layer, and selective protection is carried out on the grown i + n layer, namely, a dry film or ink and the like are generally reserved on the surface of the i + n layer, so that the etching and cleaning steps are increased, the etching and cleaning steps are complicated, the dry film or ink needs to be orderly removed by cleaning step by step, and the risk of pollution also exists. The inventor finds that since the general n layer and p layer both adopt amorphous silicon or microcrystalline silicon, i + p cannot be well removed when i + p grows on the i + n layer as a whole, and the i + n layer cannot be removed or can not be removed controllably, an isolation layer such as a dry film or ink is generally reserved on the surface of the i + n layer, so that the etching and cleaning steps are complex, and the isolation layer needs to be removed orderly by cleaning step by step, so that the whole preparation process is complicated; alternatively, it is difficult to achieve the etching of the phosphorus doped n-layer by a one-step alkaline etch without etching to the underlying intrinsic i-layer. In addition, the intermediate isolation layer, such as an organic dry film, is generally not resistant to high temperature, and has a great risk of contaminating the chamber when entering the CVD plated i + p layer.
In view of this, the technical solution of the embodiments of the present application provides a method for manufacturing a heterojunction solar cell and a heterojunction solar cell. The technical scheme of the embodiment of the application is favorable for reducing the cleaning steps, can simplify the preparation process, and reduces the pollution risk caused by the fact that the isolation layer (printing ink or dry film) enters the cavity. See below for a description of specific embodiments.
Referring to fig. 1 to 12, in some embodiments, a method for fabricating a heterojunction solar cell is provided, the method comprising:
patterning the back of the semiconductor substrate to form a first doping region and a second doping region which are arranged in a staggered mode, wherein the first doping region is provided with a first intrinsic i layer and an n-type doping layer (i + n layer), and the n-type doping layer is an oxygen-doped microcrystalline silicon layer doped with VA group elements;
forming a second intrinsic i layer and a p-type doped layer (i + p layer) on the first doped region and the second doped region, wherein the p-type doped layer is an amorphous or microcrystalline silicon layer doped with a group iiia element;
forming a patterned mask layer on the second intrinsic i layer and the p-type doped layer, exposing the second intrinsic i layer and the p-type doped layer on the first doped region through the patterned mask layer, removing the exposed second intrinsic i layer and the exposed p-type doped layer, and keeping the first intrinsic i layer and the n-type doped layer;
and removing the patterned mask layer, and forming a second intrinsic i layer and a p-type doped layer in the second doped region, thereby completing the preparation of n and p in the selective region.
According to the preparation method of the heterojunction solar cell provided by the embodiment of the invention, the formed n-type doping layer is an oxygen-doped microcrystalline silicon layer doped with VA group elements, and the formed p-type doping layer is an amorphous or microcrystalline silicon layer doped with IIIA group elements. Thus, when the second intrinsic i layer and the p-type doped layer on the first doped region are removed, an intermediate isolation layer is not required to be arranged, the second intrinsic i layer and the p-type doped layer above the first doped region can be removed in one step by utilizing the reaction difference between the n-type doped layer (oxygen-doped microcrystalline silicon layer) and the amorphous i layer (non-oxygen-doped amorphous silicon layer) and an etching solution such as an alkali solution, the first intrinsic i layer and the n-type doped layer below the first doped region can be reserved, and the first intrinsic i layer and the n-type doped layer below the first doped region can be basically prevented from being influenced when the second intrinsic i layer and the p-type doped layer above are etched by using the alkali solution. Thus, the invention can use the original less controllable non-intermediate isolation layer (such as printing ink or dry film, SiO) x Or SiN x Etc.) etching the second intrinsic i layer and the p-type doped layer becomes controllable; the invention does not need to reserve an isolation layer (such as ink or a dry film) into the cavity, reduces or avoids the pollution risk, and does not need to additionally increase the isolation layer (such as SiO) x Or SiN x Etc.) and the complicated steps of removing the isolating layer, simplifies the preparation process, has simple preparation flow and improves the production efficiencyAnd (4) rate.
According to the preparation method of the heterojunction solar cell, the i layer grows on the patterned i + n layer and covers the i + n layer, the technical effect of insulation is achieved, the p layer and the n layer do not need to be subjected to electrical insulation etching in the subsequent process, the preparation process is simplified, and the operation is convenient.
The VA group element comprises one or more of nitrogen, phosphorus, arsenic and antimony. Preferably, in this embodiment, the group VA element is phosphorus. The IIIA group elements include one or more of indium, boron, aluminum and gallium. Preferably, in this embodiment, the group IIIA element is boron.
Optionally, the n-type doped layer is an oxygen-doped microcrystalline silicon layer doped with phosphorus. Optionally, the p-type doped layer is an amorphous or microcrystalline silicon layer doped with boron.
The method provided by the embodiment of the invention is suitable for being applied to the field of solar cells and can be applied to the preparation of various solar cells, such as HBC cells and the like. The method of the present invention will be described in detail below mainly by taking an HBC cell as an example, but it will be understood by those skilled in the art that the method of the present invention is not limited to being applied to an HBC cell, but is suitably applied to various solar cells.
In the embodiment of the present invention, the semiconductor substrate may be a silicon substrate, such as a monocrystalline silicon substrate, a polycrystalline silicon substrate, or a monocrystalline silicon-like substrate, and the embodiment of the present invention is not limited to a specific type of the semiconductor substrate. The semiconductor substrate may be doped P-type or N-type, i.e. the semiconductor substrate may be a P-type or N-type semiconductor substrate. The heterojunction solar cell of the embodiment of the invention can be an N-type heterojunction solar cell or a P-type heterojunction solar cell. Illustratively, in some embodiments, the heterojunction solar cell can be an N-type heterojunction solar cell and the semiconductor substrate is an N-type silicon substrate (also referred to as an N-type silicon wafer).
In the embodiment of the invention, the semiconductor substrate comprises two oppositely arranged side surfaces, namely a front surface and a back surface; the front surface (light-receiving surface) of the semiconductor substrate is a surface facing the sun, that is, a surface facing sunlight irradiation, and the back surface (backlight surface) of the semiconductor substrate is a surface facing away from the sun.
In the preparation process of the heterojunction solar cell, the preparation of the back surface structure of the semiconductor substrate is mainly improved, and the preparation of the front surface structure of the semiconductor substrate can refer to the preparation of solar cells in related fields, which is not limited in the embodiment.
In some embodiments, a method of fabricating a heterojunction solar cell comprises:
s100, patterning the back of the semiconductor substrate to form a first doping region and a second doping region, wherein the first doping region and the second doping region are arranged in an interdigitated mode, a first intrinsic i layer and an n-type doping layer are formed in the first doping region, and the n-type doping layer is an oxygen-doped microcrystalline silicon layer doped with phosphorus. Specifically, step S100 includes:
s110, as shown in fig. 1, providing a semiconductor substrate 10, forming a first intrinsic i layer and an n-type doped layer 20 on a back surface of the semiconductor substrate 10, and forming a first intrinsic i layer and an n-type doped layer 20 on a front surface of the semiconductor substrate 10; wherein the n-type doped layer is an oxygen-doped microcrystalline silicon layer doped with phosphorus.
In the step, a double-sided plating process is performed on the semiconductor substrate to form a first intrinsic i layer and an n-type doped layer on both the front surface and the back surface of the semiconductor substrate. In this embodiment, the first intrinsic i layer and the n-type doped layer may be formed by using a conventional process for forming the intrinsic i layer and the doped layer. Illustratively, the first intrinsic i layer and the n-type doped layer may be sequentially deposited on the front and back surfaces of the semiconductor substrate using a Chemical Vapor Deposition (CVD) method. Alternatively, the chemical vapor deposition (plating) method includes, but is not limited to, PECVD or Cat-CVD. The specific operation mode and process conditions for forming the first intrinsic i layer and the n-type doped layer can be selectively controlled by those skilled in the art according to practical situations, which is not limited in this embodiment.
The n-type doped layer on the front surface of the semiconductor substrate can be used as a front passivation layer and a light-transmitting window layer.
Optionally, the provided semiconductor substrate is a textured semiconductor substrate. Illustratively, providing a semiconductor substrate includes: providing an n-type monocrystalline silicon substrate, cleaning the n-type monocrystalline silicon substrate for texturing, and forming a textured structure on the clean surface of the n-type monocrystalline silicon substrate.
Optionally, the thickness of the first intrinsic i layer is 5nm to 20 nm. Further, the thickness of the first intrinsic i layer may be 7nm to 10 nm. For example, the first intrinsic i layer may be 5nm, 6nm, 4nm, 8nm, 9nm, 10nm, 12nm, 15nm, 16nm, 18nm, 20nm, and the like.
Optionally, the thickness of the n-type doped layer may be 8nm to 200 nm. Further, the thickness of the n-type doped layer may be 10nm to 150 nm.
Optionally, the n-type doped layer is prepared by a chemical vapor deposition method. Preferably, in the process step of preparing the n-type doped layer, i.e. the n-doped oxygen-doped microcrystalline silicon layer, carbon dioxide and nitrous oxide are used as oxygen sources, and the flow ratio of the oxygen sources to silane is 1: 8-2: 1. Thus, a desired n-doped oxygen-doped microcrystalline silicon layer is easily obtained, and when the second intrinsic i layer and the p-doped layer on the first doped region are removed, the second intrinsic i layer and the p-doped layer above the first doped region can be removed in one step by using a difference in reaction between the n-doped layer (oxygen-doped microcrystalline silicon layer) and the amorphous i layer (non-oxygen-doped amorphous silicon layer) and an etching solution, and the first intrinsic i layer and the n-doped layer below the first doped region can be maintained.
S120, as shown in FIG. 2, preparing a mask on the surfaces of the first intrinsic i layer and the n-type doped layer 20 on the back surface of the semiconductor substrate 10, exposing and developing to form a patterned mask layer 31; and a mask 32 is prepared on the surfaces of the first intrinsic i layer and the n-type doped layer 20 on the front surface of the semiconductor substrate 10 and the entire mask layer on the front surface is left.
In this step, the front and back surfaces of the semiconductor substrate 10 are laminated, and the laminated film is an organic film layer (which may be referred to as a photomask) capable of or having a photosensitive development property, the back surface of the semiconductor substrate 10 is exposed and developed, and the developed area is removed to form a patterned mask layer 31; the back developing area of the semiconductor substrate is a second doping area, namely a deposition area for subsequently carrying out a p-type doping layer. A blanket exposure of the front side of the semiconductor substrate 10 is performed and a blanket layer of the mask 32 is left to protect the first intrinsic i layer and the n-doped layer 20 of the front side from being removed.
It is noted that the photomask may be required to have alkali resistance, but not to other solutions.
S130, as shown in fig. 3, the first intrinsic i layer and the n-type doped layer 20 not covered by the mask are removed to form the second doped region.
In this step, for the back surface of the semiconductor substrate 10, since a part of the first intrinsic i layer and the n-type doped layer 20 is covered by the photomask and another part of the first intrinsic i layer and the n-type doped layer 20 is not covered by the photomask, the first intrinsic i layer and the n-type doped layer 20 which are not covered by the photomask may be removed by a conventional method, and a region where the first intrinsic i layer and the n-type doped layer 20 are removed is the second doped region. For the semiconductor front side, the first intrinsic i-layer and the n-doped layer 20 are protected from being removed by the entire photomask 32.
Optionally, the sample obtained in step S120 is washed in an alkaline solution to remove the first intrinsic i layer and the n-type doped layer 20 in the area without the photomask protection after the development. The concentration or temperature of the alkali solution used in this step is not particularly limited in this embodiment, and can be selectively adjusted by those skilled in the art according to the actual situation, as long as the first intrinsic i layer and the n-type doped layer not covered by the mask can be cleaned away.
S140, as shown in fig. 4, the patterned mask layer 31 is removed to form the first intrinsic i layer and the n-type doped layer 20 in the first doped region.
The step is mainly to remove the residual photomask (patterned mask layer 31) on the back surface of the semiconductor substrate 10, so that the first doped region is only provided with the first intrinsic i layer and the n-type doped layer 20; while the entire face of the photomask 32 on the front side of the semiconductor substrate 10 remains.
Optionally, the sample obtained in step S130 is placed in a photomask solution capable of etching away the exposed photomask, so as to remove the photomask on the first intrinsic i layer and the n-type doped layer, thereby forming the first intrinsic i layer and the n-type doped layer only in the first doped region. The solution capable of etching away the photomask is a solution that does not react with silicon, that is, the solution is only capable of removing the photomask and does not react with silicon, and the specific type or operation mode of the solution is not limited in this embodiment.
S200, as shown in fig. 5, sequentially forming a second intrinsic i layer and a p-type doped layer 40 on the first doped region and the second doped region, wherein the p-type doped layer is an amorphous or microcrystalline silicon layer doped with boron; that is, the p-type doped layer may be an amorphous silicon layer doped with boron element, or the p-type doped layer may be a microcrystalline silicon layer doped with boron element.
In this step S200, a second intrinsic i layer and a p-type doped layer 40 are prepared on the back surface of the semiconductor substrate 10, and since the first doped region is provided with the first intrinsic i layer and the n-type doped layer 20 in the sample obtained in step S140, the second intrinsic i layer and the p-type doped layer 40 cover the upper surface and the side surface of the first intrinsic i layer and the n-type doped layer 20 in the first doped region, and the second intrinsic i layer and the p-type doped layer 40 cover the back surface of the semiconductor substrate 10 in the second doped region.
In this embodiment, the second intrinsic i layer and the p-type doped layer may be formed by using a conventional process for forming the intrinsic i layer and the doped layer, for example, the second intrinsic i layer and the p-type doped layer may be prepared by using the same or similar method and process conditions as those in step S110. Illustratively, the second intrinsic i layer and the p-type doped layer may be sequentially deposited on the back surface of the semiconductor substrate by using a Chemical Vapor Deposition (CVD) method. Alternatively, the chemical vapor deposition (plating) method includes, but is not limited to, PECVD or Cat-CVD. The specific operation manner and process conditions for forming the second intrinsic i layer and the p-type doped layer may refer to step S110 or be selectively adjusted and controlled by those skilled in the art according to actual situations, which is not limited in this embodiment.
Generally, in the conventional process, after the n-doped layer and the p-doped layer are formed, a process step of performing an electrical insulation treatment of the n-doped layer and the p-doped layer is further included. However, in the embodiment of the present application, in the step S200, the second intrinsic i layer may completely cover the upper surface and the side surface of the first intrinsic i layer and the n-type doped layer 20 in the first doped region, so that the p-type doped layer and the n-type doped layer formed by the subsequent deposition may be electrically insulated without adding an additional electrically insulating processing step, thereby achieving the purposes of simplifying the process and reducing the cost.
Optionally, the thickness of the second intrinsic i layer is 5nm to 20 nm. Further, the thickness of the second intrinsic i layer may be 7nm to 10 nm. For example, the second intrinsic i layer may be 5nm, 6nm, 4nm, 8nm, 9nm, 10nm, 12nm, 15nm, 16nm, 18nm, 20nm, and the like. The thickness of the second intrinsic i layer may be maintained to be the same as that of the first intrinsic i layer.
Optionally, the thickness of the p-type doped layer may be 8nm to 200 nm. Further, the thickness of the p-type doped layer may be 10nm to 150 nm.
S300, as shown in fig. 6, a patterned mask layer 31 is formed on the second intrinsic i layer and the p-type doped layer 40, the patterned mask layer 31 exposes the second intrinsic i layer and the p-type doped layer 40 on the first doped region, the exposed second intrinsic i layer and the p-type doped layer 40 are removed, and the first intrinsic i layer and the n-type doped layer 20 remain.
In step S300, the sample obtained in step S200 is subjected to film pressing, exposure and development on the back surface of the semiconductor substrate 10 to expose the second intrinsic i layer and the p-type doped layer 40 above the first intrinsic i layer and the n-type doped layer 20 formed in the first doped region, and then the sample may be placed in an etching solution (e.g., an alkaline solution) to etch away the exposed second intrinsic i layer and the p-type doped layer 40, but not the underlying first intrinsic i layer and the n-type doped layer 20. Specifically, step S300 includes:
and S310, performing film pressing on the sample obtained in the step S200 for the back surface of the semiconductor substrate 10, namely, preparing a mask on the surfaces of the second intrinsic i layer and the p-type doped layer 40, and then exposing and developing to form a patterned mask layer 31. The patterned mask layer 31 covers the second intrinsic i layer and the p-type doped layer 40 located on the second doped region and exposes the second intrinsic i layer and the p-type doped layer 40 located on the first doped region.
The operation modes and conditions of the mask preparation, exposure and development in step S310 can refer to step S120, and are not described herein again.
And S320, removing the second intrinsic i layer and the p-type doped layer 40 exposed outside (not covered by the photomask) by adopting a chemical etching mode, wherein in the first doped region, the etching rate of the second intrinsic i layer and the p-type doped layer 40 is greater than that of the n-type doped layer, so that the first intrinsic i layer and the n-type doped layer 20 below the second intrinsic i layer and the p-type doped layer 40 are reserved.
In this embodiment, in the first doped region, the manner that the second intrinsic i layer and the p-type doped layer are etched away and the first intrinsic i layer and the n layer are retained is realized, and the characteristic that the n-doped oxygen-doped microcrystalline silicon layer reacts slower with the alkaline solution than the amorphous intrinsic i layer which is not doped with oxygen is mainly utilized, so that after the amorphous intrinsic i layer on the upper layer is etched, the reaction speed with the n-doped oxygen-doped microcrystalline silicon layer is suddenly reduced, and thus the n layer on the lower layer is not excessively etched away. The chemical etching can be carried out by adopting an alkali solution, the temperature and the concentration of the alkali solution can be adjusted according to the amount of doped oxygen of the microcrystalline n-layer, and the doped oxygen can be adjusted by adjusting the flow of an oxygen source. Because the more the oxygen doping amount is, the slower the reaction speed of the microcrystalline n-layer and the alkali solution is, and the etching rate generally shows the difference of the etching rate of the solution concentration and the temperature at a certain oxygen doping ratio.
Optionally, the process conditions of the chemical etching include: etching by using alkali liquor, wherein the mass concentration of the alkali liquor is not more than 1.5%; the etching temperature is 18-35 ℃. Alternatively, the alkali solution used may be a NaOH solution, and of course, other types of alkali solutions may also be used, which is not limited in this embodiment.
When the exposed second intrinsic i layer and the p-type doped layer are etched, the concentration of the adopted alkali solution is not easy to be too high, and the etching temperature is not easy to be too high. For example, the concentration of the lye by mass can be 1.5% or less, or 1% or less, 0.8% or less, etc., and illustratively, the concentration of the lye by mass can be 1.5%, 1.2%, 1.0%, 0.9%, 0.8%, 0.7%, 0.6%, 0.5%, 0.4%, 0.3%, etc. The temperature of the etching may be 18 to 35 ℃ and further 20 to 30 ℃, and may be, for example, 18 ℃, 19 ℃, 20 ℃, 21 ℃, 22 ℃, 23 ℃, 24 ℃, 25 ℃, 26 ℃, 28 ℃, 30 ℃, 35 ℃ or the like. The concentration and the etching problem of the alkali solution can be adjusted according to the oxygen doping amount of the n-type doping layer, and in the range, the method is favorable for enabling the etching rate to be moderate, improving the production efficiency, reducing the cost and ensuring the quality of the silicon wafer.
S400, as shown in fig. 7, the patterned mask layer 31 on the back surface of the semiconductor substrate 10 is removed, the second intrinsic i layer and the p-type doped layer 40 are formed in the second doped region, and the mask 32 on the front surface of the semiconductor substrate 10 is removed.
In this step, the remaining photomask (patterned mask layer 31) on the back surface of the semiconductor substrate 10 is mainly removed, that is, the photomask in the second doped region is removed, so that the second doped region is only provided with the second intrinsic i layer and the p-type doped layer 40, thereby completing the preparation of the n-type region and the p-type region of the selective region. Meanwhile, in this step, the mask remaining on the back surface may be removed, and the entire surface mask 32 layer on the front surface of the semiconductor substrate 10 may be removed.
Alternatively, the sample obtained in step S320 may be placed in a suitable dry film removing solution capable of removing the developed film to remove the dry film on the front and back surfaces of the semiconductor substrate.
The requirement of removing the photomask in step S400, the solution or the operation condition, etc. may refer to the method of removing the photomask in step S140, and will not be described in detail here.
S500, preparing a back TCO layer on the surfaces of the first intrinsic i layer, the n-type doping layer, the second intrinsic i layer and the p-type doping layer; and preparing a metal electrode on the surface of the back TCO layer and patterning the back TCO layer and the metal electrode.
The step S500 is mainly used for preparing a metal electrode, and it should be noted that, in the embodiment of the present application, a specific operation manner and a process condition for forming the metal electrode are not limited, and may be selectively adjusted and controlled by a person skilled in the art according to an actual situation, for example, the metal electrode may be prepared by adopting a conventional manner for preparing a metal electrode in the field of solar cells. Illustratively, the step S500 may include:
s510, as shown in fig. 8, a back TCO layer 51 and a copper seed layer 60 are prepared on the back surface of the semiconductor substrate 10, and a front anti-reflection layer 52 is prepared on the front surface of the semiconductor substrate 10. Specifically, for the back surface of the semiconductor substrate 10, a back surface TCO layer 51 is formed on the surfaces of the first intrinsic i layer and the n-type doped layer 20 and the second intrinsic i layer and the p-type doped layer 40, that is, the back surface TCO layer 51 is formed on the surfaces of the first doped region and the second doped region, and the copper seed layer 60 is formed on the surface of the back surface TCO layer 51. The surfaces of the first intrinsic i layer and the n-doped layer 20 form a front anti-reflection layer 52 for the front surface of the semiconductor substrate 10.
The front anti-reflection layer 52 is a transparent conductive layer or other non-conductive anti-reflection layer, and the back TCO layer 51 is a transparent conductive layer, and the anti-reflection layer on the front side of the semiconductor substrate may be, but is not limited to, a transparent conductive layer ITO film, an IWO film or an AZO film, or a non-conductive anti-reflection layer SiN film x Thin film, SiN x O y The transparent conductive layer on the back surface of the one or more thin films may respectively include one or more of an ITO thin film, an IWO thin film or an AZO thin film, but is not limited to other transparent conductive thin films.
In this embodiment, the front anti-reflection layer 52, the back TCO layer 51 and the copper seed layer 60 may be formed by a conventional process; exemplary preparation methods of the front antireflection layer, the back TCO layer and the copper seed layer include, but are not limited to, PVD, RPD, evaporation or other film deposition methods.
Optionally, the thicknesses of the front antireflection layer and the back TCO layer can be 50-150 nm; further, the thickness of the front antireflection layer and the back TCO layer can be 70-900 nm.
Optionally, the thickness of the copper seed layer can be 50-1000 nm; further, the thickness of the copper seed layer can be 100-20 nm.
The front antireflection layer, the back TCO layer and the copper seed layer in the ranges are easy to realize, can be prepared under conventional process conditions, and are beneficial to reducing the cost and improving the production efficiency.
And S520, as shown in FIG. 9, electroplating the sample obtained in the step S510 to prepare a metal grid line electrode. Specifically, on the back surface of the semiconductor substrate 10, electroplating is performed to prepare metal electrodes 70, and the metal electrodes 70 (gate line electrodes) are disposed at intervals on the surface of the copper seed layer 60. It is noted only that in subsequent steps, the copper seed layer 60 needs to be etched away.
Optionally, the metal electrode patterning includes a first gate line electrode 71 on the first intrinsic i layer and the n-type doped layer 20, and a second gate line electrode 72 on the second intrinsic i layer and the p-type doped layer 40; that is, the metal electrode patterning includes a first gate line electrode 71 on the first doping region and a second gate line electrode 72 on the second doping region. The metal electrode may include a copper grid electrode, and the widths of the first grid electrode 71 and the second grid electrode 72 (copper grid line) may be 50 μm to 1500 μm.
Optionally, the width of the first gate line electrode may be 50 μm to 300 μm. Further, the width of the first gate line electrode may be 100 μm to 200 μm.
Optionally, the width of the second gate line electrode may be 500 μm to 1200 μm. Further, the width of the first gate line electrode may be 600 μm to 1000 μm.
Optionally, the distance between the first gate line electrode and the second gate line electrode may be 100 μm to 500 μm. Further, the interval between the first gate line electrode and the second gate line electrode may be 150 to 350 μm. Therefore, the first grid line electrode and the second grid line electrode are kept at a certain interval, and the n-type region and the p-type region can be prevented from being conducted to cause electric leakage.
S530, as shown in fig. 10, performing film lamination on the whole front surface of the semiconductor substrate 10 on the sample obtained in step S520, and then performing exposure; the sample was then placed in a stripped alkaline solution. The purpose of the step is mainly to etch the TCO layer of the grid line isolation region of the n-type region and the p-type region, and further realize isolation of the n-type region and the p-type region.
The pressing film and the dry film material or requirement in this step can refer to step S120, which is not limited in this embodiment.
And S540, as shown in FIG. 11, placing the front surface of the semiconductor substrate of the sample obtained in the step S530 in an alkaline solution capable of removing a dry film to remove the photomask on the front surface of the semiconductor substrate, and then washing and drying the semiconductor substrate to obtain the heterojunction solar cell.
In this step, the solution or the operation requirement for removing the dry film may refer to step S140, which is not limited in this embodiment.
Referring to fig. 12, in some embodiments, a heterojunction solar cell is provided, comprising: a semiconductor substrate 10;
the back surface of the semiconductor substrate 10 is sequentially provided with a doping layer, a back TCO layer 51 and a metal electrode 70, wherein the doping layer is composed of a first doping region and a second doping region, the first doping region and the second doping region are arranged in a staggered manner in an interdigital mode, the first doping region is provided with a first intrinsic i layer and an n-type doping layer 20, and the second doping region is provided with a second intrinsic i layer and a p-type doping layer 40; the metal electrode 70 includes a first gate line electrode 71 on the first doping region and a second gate line electrode 72 on the second doping region.
The front surface of the semiconductor substrate 10 is sequentially provided with a first intrinsic i layer and n-type doped layer 20, and a front anti-reflection layer 52.
It will be understood by those skilled in the art that the method for manufacturing a heterojunction solar cell is based on the same inventive concept, and the features and advantages described above with respect to the method for manufacturing a heterojunction solar cell are equally applicable to the heterojunction solar cell, and thus the heterojunction solar cell has at least the same or similar features and advantages as the method for manufacturing a heterojunction solar cell, and will not be described in detail herein.
According to the step S300 in the method provided in this embodiment of the present application, the reaction degrees of different types or different component film layers with the alkali solution are different, in order to indicate the etching degrees of the alkali solution on different types of film layers, this embodiment performs multiple sets of test verifications, and the alkali solution is used to etch different film layers, and the test results are shown in table 1 below.
TABLE 1
In table 1, α -i-1 to α -i-4 respectively represent amorphous i layer-1 (1# amorphous i layer), amorphous i layer-2 (2# amorphous i layer), amorphous i layer-3, and amorphous i layer-4; μ c-SiO x -1 to μ c-SiO x -3 is a microcrystalline n-doped oxygen layer-1 (1# microcrystalline n-doped oxygen layer), a microcrystalline n-doped oxygen layer-2, and a microcrystalline n-doped oxygen layer-3; the μ c-Si-1 to μ c-Si-3 respectively represent a microcrystalline silicon (not doped with oxygen) layer-1, a microcrystalline silicon layer-2, and a microcrystalline silicon layer-3.
As can be seen from the data in table 1, the difference between the reaction between the oxygen-doped microcrystalline n-layer and the non-oxygen-doped amorphous i-layer and the alkaline solution is utilized, so that the second intrinsic i-layer and the p-type doped layer above the first doped region are removed in one step by utilizing the characteristic that the reaction between the oxygen-doped microcrystalline silicon oxide and the alkaline solution is slower than that of the non-oxygen-doped amorphous intrinsic i-layer, and the first intrinsic i-layer and the n-type doped layer below the first doped region can be retained, that is, the first intrinsic i-layer and the n-type doped layer below the first doped region can be guaranteed not to be affected basically when the second intrinsic i-layer and the p-type doped layer above are etched by using the alkaline solution, thereby simplifying the preparation process, improving the production efficiency, and reducing or avoiding the risk of contamination.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. Further, the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of fabricating a heterojunction solar cell, the method comprising:
patterning the back of the semiconductor substrate to form a first doping region and a second doping region which are arranged in a staggered mode, wherein the first doping region is provided with a first intrinsic i layer and an n-type doping layer, and the n-type doping layer is an oxygen-doped microcrystalline silicon layer doped with VA group elements;
forming a second intrinsic i layer and a p-type doped layer on the first doped region and the second doped region, wherein the p-type doped layer is an amorphous or microcrystalline silicon layer doped with a group IIIA element;
forming a patterned mask layer on the second intrinsic i layer and the p-type doped layer, wherein the patterned mask layer exposes the second intrinsic i layer and the p-type doped layer on the first doped region, removes the exposed second intrinsic i layer and the exposed p-type doped layer, and retains the first intrinsic i layer and the exposed n-type doped layer;
and removing the patterned mask layer, and forming the second intrinsic i layer and the p-type doped layer in the second doped region.
2. The method of claim 1, wherein the patterning on the back side of the semiconductor substrate to form the first doped region and the second doped region in a staggered arrangement, the first doped region having the first intrinsic i layer and the n-type doped layer formed thereon specifically comprises:
forming the first intrinsic i layer and the n-type doped layer on the back surface of the semiconductor substrate;
preparing masks on the surfaces of the first intrinsic i layer and the n-type doped layer, and exposing and developing to form a patterned mask layer;
removing the first intrinsic i layer and the n-type doped layer which are not covered by the mask to form the second doped region;
and removing the patterned mask layer to form the first intrinsic i layer and the n-type doped layer in the first doped region.
3. The method of fabricating the heterojunction solar cell of claim 1 or 2, wherein the thickness of the first intrinsic i layer and/or the second intrinsic i layer is 5nm to 20nm, and the second intrinsic i layer covers upper and side surfaces of the first intrinsic i layer and the n-type doped layer within the first doped region.
4. The method according to claim 1, wherein a patterned mask layer is formed on the second intrinsic i layer and the p-type doped layer, the patterned mask layer exposes the second intrinsic i layer and the p-type doped layer on the first doped region, and removing the exposed second intrinsic i layer and the exposed p-type doped layer and leaving the first intrinsic i layer and the exposed n-type doped layer specifically comprises:
preparing masks on the surfaces of the second intrinsic i layer and the p-type doped layer, and exposing and developing to form a patterned mask layer;
the second intrinsic i layer and the p-type doped layer on the first doped region are exposed out of the patterned mask layer;
and removing the second intrinsic i layer and the p-type doped layer exposed outside by adopting a chemical etching mode, wherein the etching rate of the second intrinsic i layer and the p-type doped layer is greater than that of the n-type doped layer, so that the first intrinsic i layer and the n-type doped layer below the second intrinsic i layer and the p-type doped layer are reserved.
5. The method of claim 4, wherein the chemical etching process conditions comprise:
etching by using alkali liquor, wherein the mass concentration of the alkali liquor is not more than 1.5%;
the etching temperature is 18-35 ℃.
6. The method of claim 1, wherein the removing the patterned mask layer further comprises, after the second doped region is formed with the second intrinsic i layer and the p-type doped layer:
preparing back TCO layers on the surfaces of the first intrinsic i layer, the n-type doped layer, the second intrinsic i layer and the p-type doped layer;
and preparing a metal electrode on the surface of the back TCO layer and patterning the back TCO layer and the metal electrode.
7. The method of claim 6, wherein the metal electrode patterning comprises a first gate line electrode on a first intrinsic i layer and an n-type doped layer, and a second gate line electrode on a second intrinsic i layer and a p-type doped layer;
the width of the first grid line electrode is 50-300 mu m, the width of the second grid line electrode is 500-1200 mu m, and the distance between the first grid line electrode and the second grid line electrode is 100-500 mu m.
8. The method of fabricating a heterojunction solar cell of claim 1, further comprising:
forming a first intrinsic i layer and an n-type doped layer on the front surface of a semiconductor substrate;
and forming a front antireflection layer on the surfaces of the first intrinsic i layer and the n-type doped layer.
9. The method for fabricating a heterojunction solar cell according to any of claims 1 to 2 and 4 to 8, wherein the process step of forming the n-type doped layer comprises: carbon dioxide and/or nitrous oxide are used as oxygen sources, and the flow ratio of the oxygen sources to silane is 1: 8-2: 1.
10. A heterojunction solar cell, comprising:
a semiconductor substrate;
the back surface of the semiconductor substrate is sequentially provided with a doping layer, a back TCO layer and a metal electrode, wherein the doping layer consists of a first doping region and a second doping region, the first doping region and the second doping region are arranged in a staggered manner in a finger-crossing manner, the first doping region is provided with a first intrinsic i layer and an n-type doping layer, and the second doping region is provided with a second intrinsic i layer and a p-type doping layer;
the front surface of the semiconductor substrate is sequentially provided with a first intrinsic i layer, an n-type doping layer and a front surface antireflection layer.
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