MY148605A - Processes and integrated systems for engineering a substrate surface for metal deposition - Google Patents

Processes and integrated systems for engineering a substrate surface for metal deposition

Info

Publication number
MY148605A
MY148605A MYPI20090714A MY148605A MY 148605 A MY148605 A MY 148605A MY PI20090714 A MYPI20090714 A MY PI20090714A MY 148605 A MY148605 A MY 148605A
Authority
MY
Malaysia
Prior art keywords
metal
substrate surface
copper
integrated system
processes
Prior art date
Application number
Other languages
English (en)
Inventor
Thie William
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/513,446 external-priority patent/US8747960B2/en
Priority claimed from US11/513,634 external-priority patent/US8771804B2/en
Priority claimed from US11/514,038 external-priority patent/US8241701B2/en
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of MY148605A publication Critical patent/MY148605A/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
MYPI20090714 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition MY148605A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/513,446 US8747960B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide
US11/513,634 US8771804B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a copper surface for selective metal deposition
US11/514,038 US8241701B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a barrier surface for copper deposition

Publications (1)

Publication Number Publication Date
MY148605A true MY148605A (en) 2013-05-15

Family

ID=41202298

Family Applications (2)

Application Number Title Priority Date Filing Date
MYPI20090714 MY148605A (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition
MYPI2012004997A MY171542A (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition

Family Applications After (1)

Application Number Title Priority Date Filing Date
MYPI2012004997A MY171542A (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition

Country Status (5)

Country Link
JP (2) JP5489717B2 (enrdf_load_stackoverflow)
CN (2) CN101558186B (enrdf_load_stackoverflow)
MY (2) MY148605A (enrdf_load_stackoverflow)
SG (1) SG174752A1 (enrdf_load_stackoverflow)
TW (1) TWI393186B (enrdf_load_stackoverflow)

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US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US8227344B2 (en) * 2010-02-26 2012-07-24 Tokyo Electron Limited Hybrid in-situ dry cleaning of oxidized surface layers
CN103081089A (zh) * 2010-08-31 2013-05-01 东京毅力科创株式会社 半导体装置的制造方法
JP5560144B2 (ja) * 2010-08-31 2014-07-23 東京エレクトロン株式会社 半導体装置の製造方法
JP2012054306A (ja) * 2010-08-31 2012-03-15 Tokyo Electron Ltd 半導体装置の製造方法
CN102468265A (zh) * 2010-11-01 2012-05-23 中芯国际集成电路制造(上海)有限公司 连接插塞及其制作方法
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8603913B1 (en) * 2012-12-20 2013-12-10 Lam Research Corporation Porous dielectrics K value restoration by thermal treatment and or solvent treatment
US9040385B2 (en) 2013-07-24 2015-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for cleaning substrate surface for hybrid bonding
JP2017500212A (ja) * 2013-10-22 2017-01-05 トーソー エスエムディー，インク． 最適化テクスチャ処理表面と最適化の方法
CN106463412A (zh) * 2014-06-16 2017-02-22 英特尔公司 集成电路器件的金属之间的选择性扩散阻挡部
US9997405B2 (en) * 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9768060B2 (en) * 2014-10-29 2017-09-19 Applied Materials, Inc. Systems and methods for electrochemical deposition on a workpiece including removing contamination from seed layer surface prior to ECD
JP6998945B2 (ja) * 2016-10-02 2022-01-18 アプライド マテリアルズ インコーポレイテッド ルテニウムライナーと共に銅のエレクトロマイグレーションを改善するドープされた選択的な金属キャップ
JP6842159B2 (ja) * 2016-12-13 2021-03-17 サムコ株式会社 プラズマ処理方法
US10438846B2 (en) 2017-11-28 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Physical vapor deposition process for semiconductor interconnection structures
JP2019192892A (ja) 2018-04-18 2019-10-31 東京エレクトロン株式会社 処理システムおよび処理方法
KR20250109239A (ko) 2018-12-05 2025-07-16 램 리써치 코포레이션 보이드 프리 (void free) 저응력 (low stress) 충진
KR102301933B1 (ko) * 2018-12-26 2021-09-15 한양대학교 에리카산학협력단 반도체 소자의 제조 방법
CN113424308B (zh) 2019-02-13 2024-11-19 朗姆研究公司 带有抑制控制的钨特征填充
US20220344205A1 (en) * 2019-09-25 2022-10-27 Tokyo Electron Limited Substrate liquid processing method and substate liquid processing apparatus
US11555250B2 (en) * 2020-04-29 2023-01-17 Applied Materials, Inc. Organic contamination free surface machining
CN115867695A (zh) * 2020-05-08 2023-03-28 朗姆研究公司 电镀钴、镍及其合金
US20220375751A1 (en) * 2021-05-24 2022-11-24 Applied Materials, Inc. Integrated epitaxy and preclean system
CN115394911A (zh) * 2022-06-06 2022-11-25 昕原半导体(杭州)有限公司 阻变式存储器的下电极及制备方法
CN120376473A (zh) * 2025-06-26 2025-07-25 昆山科比精工设备有限公司 一种硅片镀铜前处理用转运装置

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US6475893B2 (en) * 2001-03-30 2002-11-05 International Business Machines Corporation Method for improved fabrication of salicide structures
JP2003034876A (ja) * 2001-05-11 2003-02-07 Ebara Corp 触媒処理液及び無電解めっき方法
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
US7008872B2 (en) * 2002-05-03 2006-03-07 Intel Corporation Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
US6875693B1 (en) * 2003-03-26 2005-04-05 Lsi Logic Corporation Via and metal line interface capable of reducing the incidence of electro-migration induced voids
JP2004363155A (ja) * 2003-06-02 2004-12-24 Ebara Corp 半導体装置の製造方法及びその装置
JP2005116630A (ja) * 2003-10-03 2005-04-28 Ebara Corp 配線形成方法及び装置
JP2007042662A (ja) * 2003-10-20 2007-02-15 Renesas Technology Corp 半導体装置
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JP4503356B2 (ja) * 2004-06-02 2010-07-14 東京エレクトロン株式会社 基板処理方法および半導体装置の製造方法

Also Published As

Publication number Publication date
CN101558186A (zh) 2009-10-14
JP5820870B2 (ja) 2015-11-24
JP2010503205A (ja) 2010-01-28
TW200832556A (en) 2008-08-01
CN103107120B (zh) 2016-06-08
CN101558186B (zh) 2015-01-14
SG174752A1 (en) 2011-10-28
JP5489717B2 (ja) 2014-05-14
TWI393186B (zh) 2013-04-11
JP2014099627A (ja) 2014-05-29
CN103107120A (zh) 2013-05-15
MY171542A (en) 2019-10-17

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