MX364811B - Dispositivo y método para procesar datos. - Google Patents
Dispositivo y método para procesar datos.Info
- Publication number
- MX364811B MX364811B MX2016011199A MX2016011199A MX364811B MX 364811 B MX364811 B MX 364811B MX 2016011199 A MX2016011199 A MX 2016011199A MX 2016011199 A MX2016011199 A MX 2016011199A MX 364811 B MX364811 B MX 364811B
- Authority
- MX
- Mexico
- Prior art keywords
- group
- code
- ldpc code
- processing data
- bits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Pure & Applied Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Algebra (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Esta tecnología pertenece a un dispositivo y método para procesar datos que hacen posible asegurar una buena calidad de comunicación cuando se utiliza un código de LDPC para transmitir datos. En el intercalado por grupos, un código de LDPC que tiene una longitud de código N de 64800 bits y una tasa de código r de 7/15, 9/15, 11/15, o 13/15 se intercala en una base de unidad por grupo de bits, cada grupo de bits comprende 360 bits. En el desintercalado por grupos, el código de LDPC desintercalado se restaura al orden original del mismo. Esta invención puede aplicarse cuando se lleve a cabo transmisión de datos utilizando codificación de LDPC, por ejemplo.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014042968A JP2015170912A (ja) | 2014-03-05 | 2014-03-05 | データ処理装置、及び、データ処理方法 |
PCT/JP2015/055139 WO2015133322A1 (ja) | 2014-03-05 | 2015-02-24 | データ処理装置、及び、データ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
MX2016011199A MX2016011199A (es) | 2016-11-15 |
MX364811B true MX364811B (es) | 2019-05-07 |
Family
ID=54055131
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2016011199A MX364811B (es) | 2014-03-05 | 2015-02-24 | Dispositivo y método para procesar datos. |
MX2019005297A MX2019005297A (es) | 2014-03-05 | 2016-08-29 | Dispositivo y metodo para procesar datos. |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2019005297A MX2019005297A (es) | 2014-03-05 | 2016-08-29 | Dispositivo y metodo para procesar datos. |
Country Status (5)
Country | Link |
---|---|
US (3) | US10164661B2 (es) |
JP (1) | JP2015170912A (es) |
KR (5) | KR101929146B1 (es) |
MX (2) | MX364811B (es) |
WO (1) | WO2015133322A1 (es) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150046766A1 (en) * | 2013-02-08 | 2015-02-12 | Sony Corporation | Data processing apparatus and data processing method |
EP2955855A4 (en) | 2013-02-08 | 2016-08-17 | Sony Corp | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD |
GB201312243D0 (en) * | 2013-07-08 | 2013-08-21 | Samsung Electronics Co Ltd | Non-Uniform Constellations |
KR20160064086A (ko) * | 2013-09-26 | 2016-06-07 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
JP2015156532A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170912A (ja) | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015179960A (ja) * | 2014-03-19 | 2015-10-08 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
WO2015178216A1 (ja) * | 2014-05-21 | 2015-11-26 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP6885027B2 (ja) * | 2016-11-18 | 2021-06-09 | ソニーグループ株式会社 | 送信装置、及び、送信方法 |
JP6930377B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
JP6930376B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
WO2019142681A1 (ja) * | 2018-01-18 | 2019-07-25 | ソニー株式会社 | 送信方法及び受信装置 |
US11266183B2 (en) * | 2018-03-09 | 2022-03-08 | Recovery Force, LLC | Systems and method for compression control in a wearable compression device |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1463255A1 (en) | 2003-03-25 | 2004-09-29 | Sony United Kingdom Limited | Interleaver for mapping symbols on the carriers of an OFDM system |
US7555696B2 (en) * | 2004-12-09 | 2009-06-30 | General Instrument Corporation | Method and apparatus for forward error correction in a content distribution system |
US7451361B2 (en) * | 2005-01-27 | 2008-11-11 | General Instrument Corporation | Method and apparatus for forward error correction in a content distribution system |
CN1983861B (zh) | 2005-06-21 | 2012-09-26 | 三星电子株式会社 | 通信系统中发送/接收数据的装置和方法 |
KR101435681B1 (ko) * | 2007-11-08 | 2014-09-02 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서데이터 송수신 장치 및 방법 |
EP2509270B1 (en) | 2007-11-26 | 2017-05-17 | Sony Corporation | Decoding apparatus and method for a rate 2/3 64k ldpc code |
EP2134051A1 (en) | 2008-06-13 | 2009-12-16 | THOMSON Licensing | An adaptive QAM transmission scheme for improving performance on an AWGN channel |
TWI427936B (zh) * | 2009-05-29 | 2014-02-21 | Sony Corp | 接收設備,接收方法,程式,及接收系統 |
WO2011005219A1 (en) | 2009-07-07 | 2011-01-13 | Agency For Science, Technology And Research | Novel mdm2 binding peptides and uses thereof |
US9055034B2 (en) | 2009-07-08 | 2015-06-09 | Thomson Licensing | Backward looking robust header compression receiver |
US8710483B2 (en) | 2009-07-10 | 2014-04-29 | Hewlett-Packard Development Company, L.P. | Memristive junction with intrinsic rectifier |
JP2011176645A (ja) | 2010-02-24 | 2011-09-08 | Sony Corp | データ処理装置、及びデータ処理方法 |
JP2011176783A (ja) | 2010-02-26 | 2011-09-08 | Sony Corp | データ処理装置、及びデータ処理方法 |
JP5664919B2 (ja) | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP2688173B1 (en) | 2012-07-20 | 2017-03-22 | Panasonic Intellectual Property Management Co., Ltd. | Multi-service provision with energy storage system |
KR20160064086A (ko) * | 2013-09-26 | 2016-06-07 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
KR20160061328A (ko) | 2013-09-26 | 2016-05-31 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
JP2015156532A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
-
2014
- 2014-03-05 JP JP2014042968A patent/JP2015170912A/ja active Pending
-
2015
- 2015-02-24 KR KR1020177017143A patent/KR101929146B1/ko active IP Right Grant
- 2015-02-24 KR KR1020207035175A patent/KR102322523B1/ko active IP Right Grant
- 2015-02-24 US US15/122,374 patent/US10164661B2/en active Active
- 2015-02-24 KR KR1020187035435A patent/KR102023299B1/ko active IP Right Grant
- 2015-02-24 WO PCT/JP2015/055139 patent/WO2015133322A1/ja active Application Filing
- 2015-02-24 KR KR1020167023167A patent/KR101752120B1/ko active IP Right Grant
- 2015-02-24 KR KR1020197026672A patent/KR102190362B1/ko active IP Right Grant
- 2015-02-24 MX MX2016011199A patent/MX364811B/es active IP Right Grant
-
2016
- 2016-08-29 MX MX2019005297A patent/MX2019005297A/es unknown
-
2018
- 2018-09-26 US US16/142,867 patent/US10707903B2/en active Active
-
2020
- 2020-05-21 US US16/880,009 patent/US11271595B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR101752120B1 (ko) | 2017-06-28 |
US11271595B2 (en) | 2022-03-08 |
KR20180133553A (ko) | 2018-12-14 |
KR20160124120A (ko) | 2016-10-26 |
KR102322523B1 (ko) | 2021-11-05 |
JP2015170912A (ja) | 2015-09-28 |
MX2016011199A (es) | 2016-11-15 |
US10164661B2 (en) | 2018-12-25 |
US20160373135A1 (en) | 2016-12-22 |
KR101929146B1 (ko) | 2018-12-13 |
KR102190362B1 (ko) | 2020-12-11 |
KR20200140410A (ko) | 2020-12-15 |
KR102023299B1 (ko) | 2019-11-04 |
KR20190107763A (ko) | 2019-09-20 |
KR20170076801A (ko) | 2017-07-04 |
US10707903B2 (en) | 2020-07-07 |
WO2015133322A1 (ja) | 2015-09-11 |
MX2019005297A (es) | 2019-08-12 |
US20190028122A1 (en) | 2019-01-24 |
US20200287569A1 (en) | 2020-09-10 |
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