MX347236B - Control de despeje local. - Google Patents

Control de despeje local.

Info

Publication number
MX347236B
MX347236B MX2014015349A MX2014015349A MX347236B MX 347236 B MX347236 B MX 347236B MX 2014015349 A MX2014015349 A MX 2014015349A MX 2014015349 A MX2014015349 A MX 2014015349A MX 347236 B MX347236 B MX 347236B
Authority
MX
Mexico
Prior art keywords
instruction
table entry
translation table
local
tlbs
Prior art date
Application number
MX2014015349A
Other languages
English (en)
Other versions
MX2014015349A (es
Inventor
Dan Greiner
Gustav Sittmann
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX2014015349A publication Critical patent/MX2014015349A/es
Publication of MX347236B publication Critical patent/MX347236B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Se ejecuta una instrucción implementada en una computadora. Una o más ubicaciones de la entrada de la tabla de tracción (TLB) se especifican por las instrucciones. Basándose en el control de despeje local (LC) especificando por la instrucción que es un primer valor, el procesador despeja de manera selectiva las TLB en una pluralidad de las CPU en una configuración de las estradas que corresponden a la ubicación de la entrada de la tabla de traducción determinada. Basándose en el despeje loca (LC) que es un segundo valor, el procesador despeja de manera selectiva sólo las TLB de la CPU que ejecuta la instrucción, de las entradas que corresponden a la ubicación de la entrada de la tabla de traducción determinada. Se proporciona un producto de programa de computadora, in sistema de computadora y un método implementado por computadora.
MX2014015349A 2012-06-15 2013-05-21 Control de despeje local. MX347236B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/524,612 US9182984B2 (en) 2012-06-15 2012-06-15 Local clearing control
PCT/EP2013/060346 WO2013186015A1 (en) 2012-06-15 2013-05-21 Local clearing control

Publications (2)

Publication Number Publication Date
MX2014015349A MX2014015349A (es) 2015-07-06
MX347236B true MX347236B (es) 2017-04-19

Family

ID=48485163

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2014015349A MX347236B (es) 2012-06-15 2013-05-21 Control de despeje local.

Country Status (7)

Country Link
US (1) US9182984B2 (es)
EP (1) EP2862059B1 (es)
JP (1) JP6284130B2 (es)
CN (1) CN104487940B (es)
HK (1) HK1207441A1 (es)
MX (1) MX347236B (es)
WO (1) WO2013186015A1 (es)

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CN114064517A (zh) 2021-11-19 2022-02-18 上海兆芯集成电路有限公司 指定密钥进行高速缓存写回且无效的计算机系统及方法

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Also Published As

Publication number Publication date
US20130339657A1 (en) 2013-12-19
MX2014015349A (es) 2015-07-06
EP2862059B1 (en) 2019-12-04
JP2015523650A (ja) 2015-08-13
US9182984B2 (en) 2015-11-10
HK1207441A1 (en) 2016-01-29
JP6284130B2 (ja) 2018-02-28
WO2013186015A1 (en) 2013-12-19
CN104487940A (zh) 2015-04-01
CN104487940B (zh) 2017-02-22
EP2862059A1 (en) 2015-04-22

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