MX2012008755A - Estructura y metodo para fabricar estructuras de interconexion que tienen capuchones dielectricos autoalineables. - Google Patents
Estructura y metodo para fabricar estructuras de interconexion que tienen capuchones dielectricos autoalineables.Info
- Publication number
- MX2012008755A MX2012008755A MX2012008755A MX2012008755A MX2012008755A MX 2012008755 A MX2012008755 A MX 2012008755A MX 2012008755 A MX2012008755 A MX 2012008755A MX 2012008755 A MX2012008755 A MX 2012008755A MX 2012008755 A MX2012008755 A MX 2012008755A
- Authority
- MX
- Mexico
- Prior art keywords
- metallization
- level
- cap
- layer
- ild layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/425—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/773,306 US8404582B2 (en) | 2010-05-04 | 2010-05-04 | Structure and method for manufacturing interconnect structures having self-aligned dielectric caps |
| PCT/US2011/029127 WO2011139417A2 (en) | 2010-05-04 | 2011-03-21 | Structure and method for manufacturing interconnect structures having self-aligned dielectric caps |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MX2012008755A true MX2012008755A (es) | 2012-09-07 |
Family
ID=44901409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2012008755A MX2012008755A (es) | 2010-05-04 | 2011-03-21 | Estructura y metodo para fabricar estructuras de interconexion que tienen capuchones dielectricos autoalineables. |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8404582B2 (https=) |
| EP (1) | EP2567400B1 (https=) |
| JP (1) | JP5647727B2 (https=) |
| CN (1) | CN102870212B (https=) |
| GB (1) | GB201220842D0 (https=) |
| MX (1) | MX2012008755A (https=) |
| TW (1) | TWI497591B (https=) |
| WO (1) | WO2011139417A2 (https=) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8304906B2 (en) * | 2010-05-28 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Partial air gap formation for providing interconnect isolation in integrated circuits |
| FR2960700B1 (fr) * | 2010-06-01 | 2012-05-18 | Commissariat Energie Atomique | Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias |
| TW201145493A (en) * | 2010-06-01 | 2011-12-16 | Chipmos Technologies Inc | Silicon wafer structure and multi-chip stack structure |
| US8664113B2 (en) * | 2011-04-28 | 2014-03-04 | GlobalFoundries, Inc. | Multilayer interconnect structure and method for integrated circuits |
| US9484469B2 (en) | 2014-12-16 | 2016-11-01 | International Business Machines Corporation | Thin film device with protective layer |
| US9406872B1 (en) | 2015-11-16 | 2016-08-02 | International Business Machines Corporation | Fabricating two-dimensional array of four-terminal thin film devices with surface-sensitive conductor layer |
| US9536832B1 (en) * | 2015-12-30 | 2017-01-03 | International Business Machines Corporation | Junctionless back end of the line via contact |
| US9847252B2 (en) | 2016-04-12 | 2017-12-19 | Applied Materials, Inc. | Methods for forming 2-dimensional self-aligned vias |
| KR102687971B1 (ko) | 2016-11-28 | 2024-07-25 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US10770286B2 (en) * | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
| US10515896B2 (en) * | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
| US10734234B2 (en) | 2017-12-18 | 2020-08-04 | International Business Machines Corporation | Metal cut patterning and etching to minimize interlayer dielectric layer loss |
| US11018087B2 (en) | 2018-04-25 | 2021-05-25 | International Business Machines Corporation | Metal interconnects |
| WO2019210234A1 (en) * | 2018-04-27 | 2019-10-31 | Tokyo Electron Limited | Area selective deposition for cap layer formation in advanced contacts |
| US10770395B2 (en) | 2018-11-01 | 2020-09-08 | International Business Machines Corporation | Silicon carbide and silicon nitride interconnects |
| US12131989B2 (en) | 2020-11-17 | 2024-10-29 | Intel Corporation | Vertical metal splitting using helmets and wrap-around dielectric spacers |
| US12431426B2 (en) * | 2021-08-19 | 2025-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor interconnection structures comprising a resistor device and methods of forming the same |
| CN116190209B (zh) * | 2023-02-27 | 2024-03-22 | 粤芯半导体技术股份有限公司 | 低介电常数介质层及金属互连结构的制作方法 |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8028A (en) * | 1851-04-08 | Hokse-poweb | ||
| US4206254A (en) * | 1979-02-28 | 1980-06-03 | International Business Machines Corporation | Method of selectively depositing metal on a ceramic substrate with a metallurgy pattern |
| US6153901A (en) * | 1999-01-26 | 2000-11-28 | Lucent Technologies Inc. | Integrated circuit capacitor including anchored plug |
| US6169010B1 (en) * | 1999-01-26 | 2001-01-02 | Lucent Technologies Inc. | Method for making integrated circuit capacitor including anchored plug |
| US6342733B1 (en) | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
| US6611060B1 (en) | 1999-10-04 | 2003-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device having a damascene type wiring layer |
| JP4906214B2 (ja) * | 2000-03-10 | 2012-03-28 | エフ イー アイ カンパニ | 差分スパッタリング速度を減少する装置及び方法 |
| US6975032B2 (en) * | 2002-12-16 | 2005-12-13 | International Business Machines Corporation | Copper recess process with application to selective capping and electroless plating |
| US6905964B2 (en) | 2003-01-09 | 2005-06-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer |
| JP4152202B2 (ja) * | 2003-01-24 | 2008-09-17 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2004327561A (ja) * | 2003-04-22 | 2004-11-18 | Ebara Corp | 基板処理方法及び基板処理装置 |
| US6893959B2 (en) | 2003-05-05 | 2005-05-17 | Infineon Technologies Ag | Method to form selective cap layers on metal features with narrow spaces |
| US20040248400A1 (en) | 2003-06-09 | 2004-12-09 | Kim Sun-Oo | Composite low-k dielectric structure |
| US7008871B2 (en) | 2003-07-03 | 2006-03-07 | International Business Machines Corporation | Selective capping of copper wiring |
| US7193323B2 (en) | 2003-11-18 | 2007-03-20 | International Business Machines Corporation | Electroplated CoWP composite structures as copper barrier layers |
| JP2006024698A (ja) | 2004-07-07 | 2006-01-26 | Toshiba Corp | 半導体装置及びその製造方法 |
| US7217651B2 (en) * | 2004-07-28 | 2007-05-15 | Intel Corporation | Interconnects with interlocks |
| US7390739B2 (en) * | 2005-05-18 | 2008-06-24 | Lazovsky David E | Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region |
| EP1820214A2 (en) | 2004-12-01 | 2007-08-22 | Koninklijke Philips Electronics N.V. | A method of forming an interconnect structure on an integrated circuit die |
| US7422983B2 (en) | 2005-02-24 | 2008-09-09 | International Business Machines Corporation | Ta-TaN selective removal process for integrated device fabrication |
| US7538434B2 (en) | 2005-03-08 | 2009-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper interconnection with conductive polymer layer and method of forming the same |
| JP5093479B2 (ja) * | 2005-11-24 | 2012-12-12 | 日本電気株式会社 | 多孔質絶縁膜の形成方法 |
| TW200735274A (en) * | 2005-12-29 | 2007-09-16 | Koninkl Philips Electronics Nv | Reliability improvement of metal-interconnect structure by capping spacers |
| JP2007184347A (ja) * | 2006-01-05 | 2007-07-19 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US7517736B2 (en) * | 2006-02-15 | 2009-04-14 | International Business Machines Corporation | Structure and method of chemically formed anchored metallic vias |
| US7528066B2 (en) * | 2006-03-01 | 2009-05-05 | International Business Machines Corporation | Structure and method for metal integration |
| JP2007335578A (ja) * | 2006-06-14 | 2007-12-27 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| DE102006035645B4 (de) * | 2006-07-31 | 2012-03-08 | Advanced Micro Devices, Inc. | Verfahren zum Ausbilden einer elektrisch leitfähigen Leitung in einem integrierten Schaltkreis |
| KR100752195B1 (ko) * | 2006-09-08 | 2007-08-27 | 동부일렉트로닉스 주식회사 | 반도체 소자의 배선 형성방법 |
| JP5305599B2 (ja) * | 2007-02-19 | 2013-10-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7863196B2 (en) | 2007-05-10 | 2011-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned dielectric cap |
| JP5358950B2 (ja) * | 2008-01-07 | 2013-12-04 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置 |
| US7943480B2 (en) | 2008-02-12 | 2011-05-17 | International Business Machines Corporation | Sub-lithographic dimensioned air gap formation and related structure |
-
2010
- 2010-05-04 US US12/773,306 patent/US8404582B2/en active Active
-
2011
- 2011-03-21 WO PCT/US2011/029127 patent/WO2011139417A2/en not_active Ceased
- 2011-03-21 JP JP2013509071A patent/JP5647727B2/ja not_active Expired - Fee Related
- 2011-03-21 CN CN201180022085.8A patent/CN102870212B/zh not_active Expired - Fee Related
- 2011-03-21 EP EP11777742.5A patent/EP2567400B1/en active Active
- 2011-03-21 MX MX2012008755A patent/MX2012008755A/es active IP Right Grant
- 2011-05-03 TW TW100115506A patent/TWI497591B/zh not_active IP Right Cessation
-
2012
- 2012-11-20 GB GBGB1220842.7A patent/GB201220842D0/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| TW201214560A (en) | 2012-04-01 |
| US20110272812A1 (en) | 2011-11-10 |
| TWI497591B (zh) | 2015-08-21 |
| CN102870212A (zh) | 2013-01-09 |
| CN102870212B (zh) | 2015-06-10 |
| WO2011139417A2 (en) | 2011-11-10 |
| WO2011139417A3 (en) | 2012-01-05 |
| EP2567400A4 (en) | 2017-12-27 |
| EP2567400A2 (en) | 2013-03-13 |
| GB201220842D0 (en) | 2013-01-02 |
| JP5647727B2 (ja) | 2015-01-07 |
| JP2013530519A (ja) | 2013-07-25 |
| US8404582B2 (en) | 2013-03-26 |
| EP2567400B1 (en) | 2020-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG | Grant or registration |