KR980007151A - A frame synchronization generation circuit of a car slot switch between a processor and a device - Google Patents

A frame synchronization generation circuit of a car slot switch between a processor and a device Download PDF

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Publication number
KR980007151A
KR980007151A KR1019960024063A KR19960024063A KR980007151A KR 980007151 A KR980007151 A KR 980007151A KR 1019960024063 A KR1019960024063 A KR 1019960024063A KR 19960024063 A KR19960024063 A KR 19960024063A KR 980007151 A KR980007151 A KR 980007151A
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KR
South Korea
Prior art keywords
flip
flop
output
clock
processor
Prior art date
Application number
KR1019960024063A
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Korean (ko)
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KR0182703B1 (en
Inventor
오영민
Original Assignee
유기범
대우통신 주식회사
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Priority to KR1019960024063A priority Critical patent/KR0182703B1/en
Publication of KR980007151A publication Critical patent/KR980007151A/en
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Publication of KR0182703B1 publication Critical patent/KR0182703B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 전전자 교환기에서 디바이스들과 프로세서간의 데이터들을 통신하는 타임 슬롯 스위치에서 소정 주파수의 클럭(CLK)을 이용하여 데이터 통신에 필요한 프레임 동기 신호(FS)를 생성하는 회로에 관한 것으로서, 소정 주파수의 클럭(CLK)를 계수하여 소정 주파수의 클럭(8K)을 생성 출력하는 계수 회로(1)와 : 계수회로(1)의 출력을 상기 클럭(CLK)에 동기되어 지연 출력하는 제1D 플립플롭(D1)과 제1D 플립플롭(D1)의 출력을 클럭(CLK)에 동기되어 지연 출력하는 제2D 플립플롭(D2)과: 제2D플립플롭(D2)의 출력을 반전시키는 인버터(11)와; 인버터(11) 및 제1D 플립플롭(D1)의 출력을 조합하여 상기 프레임 동기 신호(FS)로서 출력하는 앤드게이트(A1)를 구비한다. 즉, 본 발명은 타임 슬롯 스위치에서 필요한 프레임 동기 신호를 계수 및 D 플립 플롭과 논리 소자들을 이용하여 간략하게 생성할 수 있다는 효과가 있다.The present invention relates to a circuit for generating a frame synchronizing signal (FS) necessary for data communication by using a clock (CLK) of a predetermined frequency in a time slot switch for communicating data between devices and a processor in an electronic exchanger, A first D flip-flop (1) for delaying and outputting the output of the counting circuit (1) in synchronism with the clock (CLK); a counting circuit A second D flip-flop D2 for delaying and outputting the output of the first D flip-flop D1 in synchronism with the clock CLK; an inverter 11 for inverting the output of the second D flip-flop D2; And an AND gate A1 which combines the outputs of the inverter 11 and the first D flip-flop D1 and outputs the result as the frame synchronizing signal FS. That is, the present invention has an effect that a necessary frame synchronizing signal in the time slot switch can be generated by using coefficients, D flip-flops and logic elements.

Description

프로세서와 디바이스간의 카임 슬롯 스위치의 프레임 동기 발생 회로A frame synchronization generation circuit of a car slot switch between a processor and a device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 프로세서와 디바이스간의 타임 슬롯 스위치의 프레임 동기 발생 회로도.FIG. 1 is a circuit diagram of a frame synchronous generation of a time slot switch between a processor and a device according to the present invention; FIG.

제2도는 본 발명에 따른 프로세서와 디바이스간의 타임 슬롯 스위치의 프레임 동기 발생 회로의 주요 부분 파형도.FIG. 2 is a main part waveform diagram of a frame synchronization generation circuit of a time slot switch between a processor and a device according to the present invention. FIG.

Claims (1)

전전자 교환기에서 디바이스들과 프로세서간의 데이터들을 통신하는 타임 슬롯 스위치에서 소정 주파수의 클럭(CLK)을 이용하여 데이터 통신에 필요한 프레임 동기 신호(FS)를 생성하는 회로로서, 소정 주파수의 클럭(CLK)를 계수하여 소정 주파수의 클럭(8K)을 생성 출력하는 계수 회로(1)와; 상기 계수 회로(1)의 출력을 상기 클럭(CLK)에 동기되어 지연 출력하는 제1D 플립플롭(D1)과 1D 플립플롭의 출력을 상기 (CLK)에 동기되어 지연 출력하는 제2D 플립플롭(D2)과: 상기 제2D 플립플롭(D2)의 출력을 반전시키는 인버터(11)와; 상기 인버터 및 제1D 플립플롭(D1)의 출력을 조합하여 상기 프레임 동기 신호(FS)로서 출력하는 앤드 게이트(A1)를 구비하는 프로세서와 디바이스간의 타임 슬롯 스위치의 프레임 동기 발생 회로.A circuit for generating a frame synchronizing signal (FS) necessary for data communication using a clock (CLK) of a predetermined frequency in a time slot switch for communicating data between devices and a processor in an electronic exchanger, A counting circuit (1) for generating and outputting a clock (8K) of a predetermined frequency; A first D flip-flop D1 for delaying the output of the counting circuit 1 in synchronization with the clock CLK and a second D flip-flop D2 for delaying and outputting the output of the 1D flip- ); An inverter (11) for inverting an output of the second D flip-flop (D2); And a AND gate (A1) for combining the outputs of the inverter and the first D flip-flop (D1) and outputting the result as the frame synchronizing signal (FS).
KR1019960024063A 1996-06-26 1996-06-26 Frame synchronous generation switch between processor and device KR0182703B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024063A KR0182703B1 (en) 1996-06-26 1996-06-26 Frame synchronous generation switch between processor and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024063A KR0182703B1 (en) 1996-06-26 1996-06-26 Frame synchronous generation switch between processor and device

Publications (2)

Publication Number Publication Date
KR980007151A true KR980007151A (en) 1998-03-30
KR0182703B1 KR0182703B1 (en) 1999-05-15

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ID=19463589

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960024063A KR0182703B1 (en) 1996-06-26 1996-06-26 Frame synchronous generation switch between processor and device

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Publication number Publication date
KR0182703B1 (en) 1999-05-15

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