KR870005302A - Data transmission signal generation circuit - Google Patents

Data transmission signal generation circuit Download PDF

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Publication number
KR870005302A
KR870005302A KR1019850009183A KR850009183A KR870005302A KR 870005302 A KR870005302 A KR 870005302A KR 1019850009183 A KR1019850009183 A KR 1019850009183A KR 850009183 A KR850009183 A KR 850009183A KR 870005302 A KR870005302 A KR 870005302A
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KR
South Korea
Prior art keywords
signal
flop
flip
gate
data transmission
Prior art date
Application number
KR1019850009183A
Other languages
Korean (ko)
Inventor
이태상
Original Assignee
정재은
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정재은, 삼성전자 주식회사 filed Critical 정재은
Priority to KR1019850009183A priority Critical patent/KR870005302A/en
Publication of KR870005302A publication Critical patent/KR870005302A/en

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  • Oscillators With Electromechanical Resonators (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

내용 없음No content

Description

데이터전송신호 발생회로Data transmission signal generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로도,1 is a circuit diagram of the present invention,

제2도는 제1도에 따른 타이밍챠트이다.2 is a timing chart according to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,2 : D형플립플롭 3 : 발진 및 분주회로1,2: D flip-flop 3: Oscillation and frequency dividing circuit

AND : 앤드게이트 INV : 인비터AND: AND gate INV: Inverter

OR1,OR2: 오아게이트OR 1 , OR 2 : Oagate

Claims (1)

중앙처리장치의 칩선택신호(CE)에 따라 대기신호(WAIT)를 발생시키는 D형플립플롭(1)과, 상기 D형플립플롭(1)의 출력단(Q)신호와 캐랙터클록신호(CCK)의 논리곱을 취하는 앤드게이트(AND), 상기 앤드게이트(AND)의 출력신호에 따라 중앙처리장치의 억세스이네이블신호(AE)를 출력하는 D형플립플롭(2), 상기 D형플립플롭(2)의 출력단(Q)신호에 따라 상기 D형플립플롭(1)의 클리어단(CL)에 클리어신호를 공급하는 오아게이트(OR1), 상기 앤드게이트(AND)와 D형플립플롭(2) 및 오아게이트(OR1)에 인버터(INV)와 오아게이트(OR2)를 매개하여 클록신호를 각각 공급하는 발진 및 분주회로(3)를 구비하여 구성된 데이터전송신호 발생회로.D-type flip-flop 1 for generating a wait signal WAIT according to the chip selection signal CE of the central processing unit, an output terminal Q signal of the D-type flip-flop 1, and a character clock signal CCK. The AND gate AND taking the logical product of D, the D flip-flop 2 for outputting the access enable signal AE of the central processing unit according to the output signal of the AND gate AND, and the D flip-flop 2 An OR gate OR 1 for supplying a clear signal to the clear terminal CL of the D flip-flop 1 , the AND gate AND, and the D flip-flop 2 according to the output terminal Q of A data transmission signal generation circuit comprising an oscillation and division circuit (3) for supplying a clock signal to an oragate (OR 1 ) via an inverter (INV) and an oragate (OR 2 ), respectively. * 참고사항 : 최초출원 내용에 의하여 공개하는 것임.* Note: The disclosure is based on the original application.
KR1019850009183A 1985-12-06 1985-12-06 Data transmission signal generation circuit KR870005302A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850009183A KR870005302A (en) 1985-12-06 1985-12-06 Data transmission signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850009183A KR870005302A (en) 1985-12-06 1985-12-06 Data transmission signal generation circuit

Publications (1)

Publication Number Publication Date
KR870005302A true KR870005302A (en) 1987-06-08

Family

ID=69105279

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850009183A KR870005302A (en) 1985-12-06 1985-12-06 Data transmission signal generation circuit

Country Status (1)

Country Link
KR (1) KR870005302A (en)

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