KR920003650A - Timing circuit of Z80 series CPU and modem chip interface - Google Patents

Timing circuit of Z80 series CPU and modem chip interface Download PDF

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Publication number
KR920003650A
KR920003650A KR1019900011219A KR900011219A KR920003650A KR 920003650 A KR920003650 A KR 920003650A KR 1019900011219 A KR1019900011219 A KR 1019900011219A KR 900011219 A KR900011219 A KR 900011219A KR 920003650 A KR920003650 A KR 920003650A
Authority
KR
South Korea
Prior art keywords
gate
decoder
flop
flip
modem chip
Prior art date
Application number
KR1019900011219A
Other languages
Korean (ko)
Other versions
KR930003006B1 (en
Inventor
오영택
Original Assignee
정대영
대영전자공업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정대영, 대영전자공업 주식회사 filed Critical 정대영
Priority to KR1019900011219A priority Critical patent/KR930003006B1/en
Publication of KR920003650A publication Critical patent/KR920003650A/en
Application granted granted Critical
Publication of KR930003006B1 publication Critical patent/KR930003006B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Abstract

내용 없음.No content.

Description

Z80 계열 CPU와 모뎀 칩 인터페이스의 타이밍회로Timing circuit of Z80 series CPU and modem chip interface

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명의 구성도.1 is a block diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : Z80 CPU의 신호 및 I/O 어드레스 디코더 2 : 모뎀 칩1: Z80 CPU signal and I / O address decoder 2: Modem chip

3, 4, 5, 6 : OR게이트 7, 9 : D플립플롭3, 4, 5, 6: OR gate 7, 9: D flip flop

8 : NOT게이트 10 : 쿼드(Quad)삼상버퍼8: NOT gate 10: Quad three-phase buffer

11 : 옥탈(Ocatl)삼상버퍼11: Octal three-phase buffer

Claims (1)

Z80 CPU의 신호 및 I/O(입력/출력) 어드레스를 디코딩하기 위한 디코더(1), 상기 디코더(1)에 연결된 제1, 제 2 OR게이트(3, 4)와 제 1 D플립플롭(7), 상기 디코더(1)에 연결되어 데이터 및 반전된 클럭을 수신하는 제 2 D플립플롭(9), 상기 제 1 OR게이트(3)와 상기 제 1 D플립플롭(7)의 출력단자(Q)에 연결된 제 3 OR게이트(5), 상기 제 1 D플립플롭(9)의 반전출력단자(/Q)와 상기 제 2 OR게이트(4)에 연결된 제 4 OR게이트(6), 상기 디코더(1)에 연결된 옥탈삼상버퍼(11)와 쿼드삼상버퍼(10), 및 상기 디코더(1)와 상기 옥탈삼상버터(11)와 상기 쿼드삼상버퍼(10)와 상기 제 2 D플립플롭(9)과 상기 제 4 OR게이트(6)에 연결된 모뎀 칩회로(2)로 구성된 것을 특징으로 하는 타이밍 회로.A decoder 1 for decoding the signal and the I / O (input / output) address of the Z80 CPU, the first and second OR gates 3 and 4 connected to the decoder 1 and the first D flip-flop 7 ), A second D flip-flop 9 connected to the decoder 1 to receive data and an inverted clock, and an output terminal Q of the first OR gate 3 and the first D flip-flop 7. A third OR gate 5 connected to the second OR gate 5, an inverted output terminal / Q of the first D flip-flop 9, a fourth OR gate 6 connected to the second OR gate 4, and the decoder Octal three-phase buffer (11) and quad three-phase buffer (10) connected to the decoder, the decoder (1) and the octal three-phase buffer (11), the quad three-phase buffer (10) and the second D flip-flop (9) And a modem chip circuit (2) connected to the fourth OR gate (6). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900011219A 1990-07-23 1990-07-23 Timing circuit of modem chip interface KR930003006B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900011219A KR930003006B1 (en) 1990-07-23 1990-07-23 Timing circuit of modem chip interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900011219A KR930003006B1 (en) 1990-07-23 1990-07-23 Timing circuit of modem chip interface

Publications (2)

Publication Number Publication Date
KR920003650A true KR920003650A (en) 1992-02-29
KR930003006B1 KR930003006B1 (en) 1993-04-16

Family

ID=19301604

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900011219A KR930003006B1 (en) 1990-07-23 1990-07-23 Timing circuit of modem chip interface

Country Status (1)

Country Link
KR (1) KR930003006B1 (en)

Also Published As

Publication number Publication date
KR930003006B1 (en) 1993-04-16

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