KR850001650A - Frequency multiplier circuit - Google Patents

Frequency multiplier circuit Download PDF

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Publication number
KR850001650A
KR850001650A KR1019830003446A KR830003446A KR850001650A KR 850001650 A KR850001650 A KR 850001650A KR 1019830003446 A KR1019830003446 A KR 1019830003446A KR 830003446 A KR830003446 A KR 830003446A KR 850001650 A KR850001650 A KR 850001650A
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KR
South Korea
Prior art keywords
frequency multiplier
multiplier circuit
circuit
frequency
operating
Prior art date
Application number
KR1019830003446A
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Korean (ko)
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KR850000674B1 (en
Inventor
정봉영
Original Assignee
강진구
삼성반도체통신 주식회사
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Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019830003446A priority Critical patent/KR850000674B1/en
Publication of KR850001650A publication Critical patent/KR850001650A/en
Application granted granted Critical
Publication of KR850000674B1 publication Critical patent/KR850000674B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Abstract

내용 없음No content

Description

주파수체배기 회로Frequency multiplier circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 고주파수(2f) 및 저주파수(f)에서 동작하는 주파수체배기의 블럭도. 제3도(1)-(4)는 제2도의 각 단자의 입출력 파형도.2 is a block diagram of a frequency multiplier operating at high frequency (2f) and low frequency (f) in accordance with the present invention. 3 (1)-(4) are input / output waveform diagrams of respective terminals shown in FIG.

Claims (3)

주파수체배 회로에 있어서, 익스클루시이브 노아게이트(10)와 T형 플립플롭(7) 및 짝수개의 인버어터(8,9)를 사용하여 주파수 체배기를 구성함을 특징으로 하는 주파수 체배기회로.A frequency multiplier circuit comprising a frequency multiplier comprising an exclusive no-gate (10), a T-type flip-flop (7), and an even number of inverters (8, 9). 제1항에 있어서, 인버어터(8,9)의 사이에 콘덴서(C1,C2)를 접속하여 시간지연(ΔT2)을 시킴을 특징으로 하는 주파수 체배기 회로.The method of claim 1, wherein the inverter (8, 9) connected to the capacitor (C 1, C 2) between the time-delay frequency multiplier circuit characterized by a Sikkim (ΔT2) of the. 고주파수와 저주파수를 동시에 사용하는 회로에 있어서 주파수체배회로(3)를 사용하여 고주파수에서 작동하는 회로(4)와 저주파수에서 작동하는 회로(2)를 동시에 사용할 수 있음을 특징으로 하는 주파수 체배기 회로.A frequency multiplier circuit characterized in that, in a circuit using both high and low frequencies simultaneously, a frequency multiplier circuit (3) can be used to simultaneously operate a circuit (4) operating at a high frequency and a circuit (2) operating at a low frequency. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019830003446A 1983-07-21 1983-07-21 Firequency multiplier KR850000674B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019830003446A KR850000674B1 (en) 1983-07-21 1983-07-21 Firequency multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019830003446A KR850000674B1 (en) 1983-07-21 1983-07-21 Firequency multiplier

Publications (2)

Publication Number Publication Date
KR850001650A true KR850001650A (en) 1985-03-30
KR850000674B1 KR850000674B1 (en) 1985-05-09

Family

ID=19229533

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830003446A KR850000674B1 (en) 1983-07-21 1983-07-21 Firequency multiplier

Country Status (1)

Country Link
KR (1) KR850000674B1 (en)

Also Published As

Publication number Publication date
KR850000674B1 (en) 1985-05-09

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