KR890011191A - Frequency drain circuit - Google Patents

Frequency drain circuit Download PDF

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Publication number
KR890011191A
KR890011191A KR1019870015165A KR870015165A KR890011191A KR 890011191 A KR890011191 A KR 890011191A KR 1019870015165 A KR1019870015165 A KR 1019870015165A KR 870015165 A KR870015165 A KR 870015165A KR 890011191 A KR890011191 A KR 890011191A
Authority
KR
South Korea
Prior art keywords
frequency
drain circuit
frequency drain
delaying
inverter
Prior art date
Application number
KR1019870015165A
Other languages
Korean (ko)
Other versions
KR900005300B1 (en
Inventor
허찬
서민호
진태훈
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870015165A priority Critical patent/KR900005300B1/en
Publication of KR890011191A publication Critical patent/KR890011191A/en
Application granted granted Critical
Publication of KR900005300B1 publication Critical patent/KR900005300B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Transmitters (AREA)

Abstract

내용 없음No content

Description

주파수 채배회로Frequency drain circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 블럭도.1 is a block diagram of the present invention.

제2도는 본 발명의 상세회로도.2 is a detailed circuit diagram of the present invention.

제3도는 제2도의 각부 파형도.3 is a waveform diagram of each part of FIG.

Claims (1)

인버어트(G0-G4)를 통해 기준주파수(FR)를 전달지연 및 반전시키고 콘덴서(G0)의 충방전에 의해 기준 주파수(FR)를 지연시키는 지연부(10)와, 지연된 주파수(FD)와 기본 주파수(FR)를 익수클루시브 노아시키고 인버어터(G6-G7)를 통해 버퍼링시키는 논리부(20)로 이루어져서, 기본주파수(FR)보다 2채배된 주파수를 출력하는 것을 특징으로 하는 주파수 채배회로.A delay unit 10 for delaying and inverting the transmission of the reference frequency F R through the inverter G 0 -G 4 and delaying the reference frequency F R by charging and discharging the capacitor G 0 , Frequency (F D ) and the fundamental frequency (F R ) is made up of a logic part 20 to be submerged inclusive and buffered through the inverter (G 6 -G 7 ), the frequency doubled than the fundamental frequency (F R ) Frequency multiplier circuit, characterized in that for outputting. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870015165A 1987-12-28 1987-12-28 Frequency multiplying circuit KR900005300B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870015165A KR900005300B1 (en) 1987-12-28 1987-12-28 Frequency multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870015165A KR900005300B1 (en) 1987-12-28 1987-12-28 Frequency multiplying circuit

Publications (2)

Publication Number Publication Date
KR890011191A true KR890011191A (en) 1989-08-14
KR900005300B1 KR900005300B1 (en) 1990-07-27

Family

ID=19267526

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870015165A KR900005300B1 (en) 1987-12-28 1987-12-28 Frequency multiplying circuit

Country Status (1)

Country Link
KR (1) KR900005300B1 (en)

Also Published As

Publication number Publication date
KR900005300B1 (en) 1990-07-27

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