KR920001837A - PCM Clock Generation Circuit - Google Patents

PCM Clock Generation Circuit Download PDF

Info

Publication number
KR920001837A
KR920001837A KR1019900008122A KR900008122A KR920001837A KR 920001837 A KR920001837 A KR 920001837A KR 1019900008122 A KR1019900008122 A KR 1019900008122A KR 900008122 A KR900008122 A KR 900008122A KR 920001837 A KR920001837 A KR 920001837A
Authority
KR
South Korea
Prior art keywords
clock
pcm
output terminal
flop
flip
Prior art date
Application number
KR1019900008122A
Other languages
Korean (ko)
Other versions
KR930002256B1 (en
Inventor
박상률
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019900008122A priority Critical patent/KR930002256B1/en
Publication of KR920001837A publication Critical patent/KR920001837A/en
Application granted granted Critical
Publication of KR930002256B1 publication Critical patent/KR930002256B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음.No content.

Description

PCM클럭 발생회로PCM Clock Generation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 구성을 나타낸 회로도.1 is a circuit diagram showing the configuration of the present invention.

제2도는 제1도의 각부분의 신호파형도.2 is a signal waveform diagram of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 내지 4 : 플립플롭1 to 4: flip-flop

5,6 : 카운터 7 : 인버터5,6: counter 7: inverter

8 : OR 게이트 9 : 점프컨넥터8: OR gate 9: Jump connector

10 : 클럭소스 11 : 1/2 분주회로10: clock source 11: 1/2 division circuit

12 : 1/4분주회로 l3 : 카운터 회로12: 1/4 division circuit l3: counter circuit

L1 : 인덕터L1: Inductor

Claims (4)

노이즈 제거를 위해 페라이트 비드를 첨가하는 클럭소스(10), 상기 클럭소스(10)의 출력단에 연졀되어 불필요한 노이즈를 제거하는 인덕터(L1), 상기 인덕터(L1)에 연결되어 상기 클럭소스(10)로부터 출력되는 클럭신호에 대해 1/2 분주된 신호를 출력하는 1/2 분주수단(11), 상기 1/2 분주수단(11)에 연결되어 상기클럭소스(10)로부터 출력되는 클럭신호에 대해 1/4 분주된 신호를 출력하는 1/4 분주수단(12), 상기 1/4 분주수단(12)에 연결되어 클럭신호를 선택할 수 있도록 하는 점프컨넥터(5), 상기 점프컨넥터(9)에 연결된 카우터 수단(13)으로 구성되어 8KHz의 PCM 샘플링 주파수를 출력하는 것을 특징으로 하는 PCM 클럭 발생회로.A clock source 10 to which ferrite beads are added to remove noise, an inductor L1 connected to an output terminal of the clock source 10 to remove unnecessary noise, and a clock source 10 connected to the inductor L1 The clock signal output from the clock source 10 connected to the 1/2 frequency divider 11 and the 1/2 frequency divider 11 for outputting a signal divided by 1/2 with respect to the clock signal output from the A 1/4 division means 12 for outputting a 1/4 divided signal, a jump connector 5 connected to the 1/4 division means 12 to select a clock signal, and a jump connector 9 PCM clock generating circuit, characterized in that it is composed of connected counter means (13) to output a PCM sampling frequency of 8KHz. 제1항에 있어서, 상기 카우터 수단(13)의 출력단에 연결된 인버터(7), 상기 인버터(7)의 출력단 및 상기 1/4 분주수단(12)의 반전 출력단에 연결된 OR 게이트(8)를 더 포함하여 PCM 스위칭 IC 싱크클럭을 출력하는 것을 특징로 하는 PCM 클럭 발생회로.2. The OR gate (8) connected to the output terminal of the counter means (13), the output terminal of the inverter (7) and the inverting output terminal of the quarter distributing means (12). PCM clock generating circuit further comprises a PCM switching IC sink clock. 제1항에 있어서, 상기 1/2 분주수단(11) 및 1/4 분주수단(12)은 J-K 플립플롭, 상기 J-K 플립플롭의 출력단에 데이터 입력단이 연결되고 상기 J-K 플립플롭의 클럭을 클럭 입력으로 하는 D플립플롭으로 구성된 것을 특징으로 하는 PCM 클럭 발생회로.The JK flip-flop is connected to an output terminal of the JK flip-flop, and the clock of the JK flip-flop is clocked. A PCM clock generation circuit comprising a D flip flop. 제1항에 있어서, 상기 카운터 수단(13)은 제1카운터(5), 상기 제1카운터(5)의 출력단(RCO) 및 클럭 입력단(CLK)에 입력단(ENT) 및 클럭 입력단(CLK)이 연결된 제2카운터(6)로 구성된 것을 특징으로 하는 PCM 클럭 발생회로.According to claim 1, The counter means 13 has a first counter 5, the output terminal (RCO) and the clock input terminal (CLK) of the input terminal (ENT) and the clock input terminal (CLK) PCM clock generation circuit, characterized in that consisting of a second counter (6) connected. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900008122A 1990-06-01 1990-06-01 Pcm clock generating circuit KR930002256B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900008122A KR930002256B1 (en) 1990-06-01 1990-06-01 Pcm clock generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900008122A KR930002256B1 (en) 1990-06-01 1990-06-01 Pcm clock generating circuit

Publications (2)

Publication Number Publication Date
KR920001837A true KR920001837A (en) 1992-01-30
KR930002256B1 KR930002256B1 (en) 1993-03-27

Family

ID=19299719

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900008122A KR930002256B1 (en) 1990-06-01 1990-06-01 Pcm clock generating circuit

Country Status (1)

Country Link
KR (1) KR930002256B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382702B1 (en) * 2000-09-18 2003-05-09 주식회사 엘지화학 Method for preparing organic silicate polymer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382702B1 (en) * 2000-09-18 2003-05-09 주식회사 엘지화학 Method for preparing organic silicate polymer

Also Published As

Publication number Publication date
KR930002256B1 (en) 1993-03-27

Similar Documents

Publication Publication Date Title
KR920001850A (en) Flip-flop with scan path
KR920001518A (en) Semiconductor integrated circuit
KR860001637A (en) Frequency conversion circuit
KR960018901A (en) How to form a feedback latch and a feedback action on the feedback latch
KR920001837A (en) PCM Clock Generation Circuit
KR910007266A (en) Clock and Control Signal Generation Circuit
KR960016152A (en) Phase comparator
KR910013764A (en) Polarotar Pulse Generator Circuit of Satellite Broadcasting Receiver
KR900005237B1 (en) Digital data transmittion circuit by pwm coding/decoding
KR900011150A (en) T flip flop which can set initial value
KR940012090A (en) Clock divider
KR910002121A (en) Frequency Variable Variable PWM Signal Generation Circuit
KR970014566A (en) Pulse generator circuit
KR930022729A (en) 2 times operating frequency regeneration circuit
KR920007464A (en) Horizontal Synchronization Signal Matching Circuit
KR940003188A (en) Synchronous Counter Circuit
KR870005302A (en) Data transmission signal generation circuit
KR920001839A (en) System Clock Generation Circuit of Digital System
KR920009086A (en) Phase comparison circuit
KR980006841A (en) A clock generation circuit
KR960028054A (en) Apparatus and method for generating and receiving basic clock of additional communication system
KR960006272A (en) Primary / dependent flip-flop
KR19990050431A (en) 5-division circuit with duty ratio of output waveform 1: 1
KR960039627A (en) Input buffer of synchronous memory device
KR910015112A (en) Oscillator (VCO)

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030218

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee