KR920007464A - Horizontal Synchronization Signal Matching Circuit - Google Patents

Horizontal Synchronization Signal Matching Circuit Download PDF

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Publication number
KR920007464A
KR920007464A KR1019900014402A KR900014402A KR920007464A KR 920007464 A KR920007464 A KR 920007464A KR 1019900014402 A KR1019900014402 A KR 1019900014402A KR 900014402 A KR900014402 A KR 900014402A KR 920007464 A KR920007464 A KR 920007464A
Authority
KR
South Korea
Prior art keywords
nmos
inverter
gate
character information
matching circuit
Prior art date
Application number
KR1019900014402A
Other languages
Korean (ko)
Other versions
KR930005604B1 (en
Inventor
성기덕
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900014402A priority Critical patent/KR930005604B1/en
Publication of KR920007464A publication Critical patent/KR920007464A/en
Application granted granted Critical
Publication of KR930005604B1 publication Critical patent/KR930005604B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

내용 없음.No content.

Description

수평동기신호 일치화회로Horizontal Synchronization Signal Matching Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 일반적인 수평동기신호 일치화회로도.1 is a general horizontal synchronization signal matching circuit.

제2도의 (a) 내지 (e)는 제1도 및 제3도에서 사용되는 각종 클럭신호의 파형도이고, (f), (g)는 수평동기신호(), ()에 대한 파형도.(A) to (e) of FIG. 2 are waveform diagrams of various clock signals used in FIGS. 1 and 3, and (f) and (g) are horizontal synchronization signals ( ), ( Waveform diagram for).

제3도는 본 발명의 수평동기신호 일치화회로도.3 is a horizontal synchronization signal matching circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 디티피 2 : 문자정보화면발생기1: DTP2: Character information screen generator

NM1-NM6 : 엔모스 I1-I5 : 인터버NM1-NM6: NMOS I1-I5: Interver

Claims (1)

디티피(1) 및 문자정보화면발생기(2)로 구성된 문자정보 표시시스템에 있어서, 상기 문자정보화면발생기(2)의 수평동기신호단자() 를 엔모스(NM1), 노아게이트(NR1), 엔모스(NM2), 인버터(I1), 엔모스(NM4), 인버터(I3), 엔모스(NM5) 및 인버터(I4)를 연속적으로 통해 상기 디티피(1)의 수평동기신호단자()에 접속하되, 상기 인버터(I1), (I4)의 출력단자를 엔모스(NM3), (NM6)를 각기 통해 상기 노아게이트(NR1), 인터버(I3)의 출력단자에 각각 접속하고, 상기 문자 정보화면발생기(2)의 클럭신호단자(PCK1)를 엔모스(NM1)의 게이트 및 인버터(I2), 엔모스(NM4)의 게이트 및 인버터(I5)를 각기 통해 상기 엔모스(NM3), (NM6)의 게이트에 접속함과 아울러, 클럭신호단자(PXCK2), (CK1)를 상기 엔모스(NM2), (NM5)게이트에 각각 접속하고, 리세트단자(RE)를 상기 노아게이트(NR1)의 일측입력단자에 접속하여 구성된 것을 특징으로 하는 수평동기신호 일치화회로.In a character information display system composed of a DTP1 and a character information screen generator 2, a horizontal synchronous signal terminal of the character information screen generator 2 ( ) Through NMOS (NM1), NOR gate (NR1), NMOS (NM2), inverter (I1), NMOS (NM4), inverter (I3), NMOS (NM5), and inverter (I4) Horizontal synchronization signal terminal of the DTP (1) The output terminals of the inverters I1 and I4 are connected to the output terminals of the NOR gate NR1 and the interlock I3 through the NMOS NM3 and NM6, respectively. The clock signal terminal PCK1 of the character information screen generator 2 is connected to the gate of the NMOS NM1 and the inverter I2, and the gate of the NMOS NM4 and the inverter I5 respectively. And (NM6), the clock signal terminals PXCK2 and (CK1) are connected to the NMOS and NM5 gates, and the reset terminal RE is connected to the NOA gate. A horizontal synchronous signal matching circuit characterized in that it is connected to one input terminal of NR1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014402A 1990-09-12 1990-09-12 Horizontal synchronizing signal coincidence circuit KR930005604B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900014402A KR930005604B1 (en) 1990-09-12 1990-09-12 Horizontal synchronizing signal coincidence circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900014402A KR930005604B1 (en) 1990-09-12 1990-09-12 Horizontal synchronizing signal coincidence circuit

Publications (2)

Publication Number Publication Date
KR920007464A true KR920007464A (en) 1992-04-28
KR930005604B1 KR930005604B1 (en) 1993-06-23

Family

ID=19303518

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014402A KR930005604B1 (en) 1990-09-12 1990-09-12 Horizontal synchronizing signal coincidence circuit

Country Status (1)

Country Link
KR (1) KR930005604B1 (en)

Also Published As

Publication number Publication date
KR930005604B1 (en) 1993-06-23

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