JPH06291615A - Interface circuit - Google Patents

Abstract

PURPOSE:To exactly latch data concerning the interface circuit to exchange data between an IC and an external terminal. CONSTITUTION:This interface circuit is composed of flip-flops 1, 6, 8 and 12, buffers 2, 4, 5 and 11, inverters 3 and 7 and external terminal 10. Even when input data can not be properly latched by the delay time of the external terminal and the buffers, a clock MCK used for the external terminal is returned again and fetched as a clock CKB and the delay time caused by the buffers is absorbed so that proper data can be latched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit for exchanging data between an IC and an external element such as a memory.

[0002]

2. Description of the Related Art In recent years, the speed of clocks in integrated circuits has been remarkably increased, and an interface circuit capable of performing correct data transmission without depending on a delay time of a buffer or an access time of an external element has been emphasized. There is.

A conventional interface circuit will be described below with reference to FIGS. 3 and 4. In FIG. 3, reference numerals 1, 6 and 8 are flip-flops having an internal delay time td. 2,
Buffers 4 and 5 have a delay time of tdbuf. 3,
Reference numeral 7 is an inverter having a delay time tdinv. 9 is I
Represents C, 10 is hold time tdis, access time tac
, An external device with an output indefinite period tnd.

The operation of the interface circuit configured as described above will be described below with reference to FIG.

FIG. 4 is a timing chart of the conventional example shown in FIG. First, the data a is latched in the flip-flop 1 with the clock CKA. The input signal b of the external element 10 is taken into the external element 10 at the clock MCK with the delay time of the flip-flop 1 and the buffer 2. The output signal c of the external element 10 starts to be output after the access time tac, and the accuracy of the output is guaranteed for the hold time tdis from the next rising edge of the clock MCK.

The input signal d of the flip-flop 6 is delayed by tdbuf time with respect to c by the buffer 5. The input signal d is latched by the flip-flop 6 with the inverted clock CKB of the clock CKA. Finally, the flip-flop 8 outputs the data f in synchronization with the clock CKA.

[0007]

However, in the above configuration, when the difference between the clock period and the access time of the external element is small, and the delay time of the buffer varies depending on the diffusion process of the semiconductor, there is a problem that a mislatch occurs. Had a point. For example, in the configuration of FIG. 3, the access time as an external element is 25 ns, the hold time is 6 ns,
Assuming a FIFO memory with an output indefinite period of 19 ns, the clock cycle is 35 ns, the buffer delay time is 2 ns, the inverter delay time is 5 ns, and the flip-flop delay time is 8 ns. Then, the correct data is latched in the flip-flop 6 by the clock CKB.

However, in the same configuration, when the delay time of the buffer is 5 ns, the timing chart shown in FIG. 5 is obtained and the input data d is generated at the rising edge of the clock CKB.
Is not fixed, correct data is not latched in the flip-flop 6, resulting in a miss latch.

In view of the above-mentioned problems, the present invention is an interface for latching correct data by absorbing the delay time of the buffer even when mis-latching occurs due to variations in the access time of the external element and the delay time of the buffer. A circuit is provided.

[0010]

In order to solve the above problems, the interface circuit of the present invention comprises a first flip-flop for outputting data to an external device having an input signal as data and a clock input as an internal clock signal. A first buffer that receives the output signal of the first flip-flop, a first inverter that receives the internal clock signal, and a second buffer that receives the output signal of the first inverter. And input the output signal of the first buffer,
An external element that receives the output signal of the second buffer as a clock input, a third buffer that receives the output signal of the second buffer, a fourth buffer that receives the output signal of the external element, and a fourth buffer. A second flip-flop for inputting data to the IC, a second flip-flop for inputting data to the IC, a second inverter for inputting the output signal of the buffer of FIG. A third flip-flop which receives the output signal of the second flip-flop and receives the output signal of the second inverter as a clock input;
It is composed of a fourth flip-flop which receives the output signal of the third flip-flop and receives the internal clock signal as a clock input.

[0011]

According to the present invention, with the above configuration, the data to be output to the external element is latched, the obtained data and the inverted clock are output to the external element, and the clock used by the external element is re-introduced into the internal clock. By latching the data output from the external element and inputting the latched data to the IC in synchronization with the internal clock, the delay time of the buffer can be absorbed and the correct data can be latched.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An interface circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of an interface circuit of the present invention. In FIG. 1, reference numerals 1, 6, 8, 12 are flip-flops having a delay time td. 2, 4, 5 and 11 are delay time tdbuf
Buffers 3 and 7 are inverters with delay time tdinv. 9 indicates IC, 10 indicates hold time
It is an external device with tdis, access time tac, and output indefinite period tnd.

The operation of the interface circuit configured as described above will be described below with reference to FIG.

FIG. 2 is a timing chart of an embodiment of the interface circuit shown in FIG. First, the data a is latched in the flip-flop 1 with the clock CKA. The input signal b of the external element 10 is accompanied by the delay time of the flip-flop 1 and the buffer 2, and the clock M
It is taken into the external element 10 by CK. The output signal c of the external element 10 starts to be output after the access time tac, and the accuracy of the output is guaranteed for the hold time tdis from the next rising edge of the clock MCK. The input signal d of the flip-flop 12 is delayed by the delay time tdbuf of the buffer 11 with respect to the output signal c of the external element 10, but the clock CK
B is also delayed by the delay time tdbuf of the buffer 5. as a result,
The delay time of the buffer can be absorbed, and the correct data is latched in the flip-flop 12. The flip-flop 6 latches the input signal e with the inverted clock CKC that is not delayed by the buffer. Finally, the flip-flop 8 latches the input signal f with the clock CKA and outputs the data g.

As described above, according to this embodiment, by inserting the buffer 5 for taking in the clock MCK used in the external element again and the flip-flop 12 latched by the output signal CKB of the buffer 5, The delay time of the buffer depends on the semiconductor diffusion process.
Even if it varies from time to time, the delay time of the buffer can be absorbed and correct data can be latched by utilizing the property that the delay time of the buffer in the same IC has a very small variation.

[0016]

As described above, according to the present invention, the delay due to the buffer of data can be absorbed by the above configuration,
In particular, when the difference between the clock period and the access time of the external element is small and the delay time of the buffer greatly varies depending on the diffusion process of the semiconductor, its practical effect is great.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an interface circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the interface circuit.

FIG. 3 is a circuit diagram showing an example of a conventional interface circuit.

FIG. 4 is a timing chart for explaining the operation of the circuit.

FIG. 5 is a timing chart when mislatch occurs in the same circuit.

[Explanation of symbols]

 1, 6, 8, 12 Flip-flops 2, 4, 5, 11 Buffers 3, 7 Inverter 9 IC 10 External element

Claims (1)

[Claims] 1. A first flip-flop for inputting a data signal and a clock signal, a first buffer for inputting an output signal of the first flip-flop, and an internal clock signal are input through a first inverter. A second buffer, an external element that receives the output signal of the first buffer as an input, and an output signal of the second buffer as a clock input, and a third buffer that receives the output signal of the second buffer A fourth buffer for inputting the output signal of the external element, a second flip-flop for inputting the output signal of the fourth buffer and a clock input for the output signal of the third buffer, and the internal clock A signal is input through a second flip-flop, a third flip-flop that receives the output signal of the second inverter as a clock input, and the third flip-flop. Input the output signal of the lip flop,
An interface circuit comprising a fourth flip-flop that receives the internal clock signal as a clock input.